Samsung Electronics Co., Ltd.

Sang-Ho Song

Ki-Nam Kim

Yoo-Sang Hwang

Ki-nam Kim

Won-suk Yang

Tae Young Chung

Byung Jun Park

Hong-sik Jeong

Hyung-Soo Uh

Sung-Ho Jang

Sung-Sam Lee

Min-Young Shim

Min-Sung Kang

Won-Tae Park

According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

Semiconductor device and method of manufacturing the same

A method for fabricating a capacitor of a semiconductor device, and a capacitor made in accordance with the method, wherein the method includes forming a plate electrode polysilicon layer on a semiconductor substrate having a cell array region and a core/peripheral circuit region. The plate electrode polysilicon layer in the cell array region is patterned to form an opening, wherein the inner wall of the opening is used as a plate electrode. After forming a dielectric layer in the opening, a storage node is formed as a spacer on the dielectric layer on the inner wall of the opening. The plate electrode polysilicon layer in the core/peripheral circuit region remains to provide the same height between the cell array region where the cell capacitor is formed and the core/peripheral circuit region.

Method for fabricating a capacitor of a semiconductor device and a capacitor made thereby

An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Bit line landing pad and borderless contact on bit line stud with localized etch stop layer formed in void region, and manufacturing method thereof

Bit line pad and borderless contact on bit line stud with localized etch stop layer formed in an undermined region

A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve &ldquo;lift-off&rdquo; problems, twin-bit failures, and misalignment.

DRAM cell capacitor and manufacturing method thereof

A method for fabricating a capacitor of a semiconductor device, and a capacitor made in accordance with the method are disclosed. The method includes forming a plate electrode polysilicon layer on a semiconductor substrate having a cell array region and a core/peripheral circuit region. The plate electrode polysilicon layer in the cell array region is patterned to form an opening, wherein the inner wall of the opening is used as a plate electrode. After forming a dielectric layer in the opening, a storage node is formed as a spacer on the dielectric layer on the inner wall of the opening. The plate electrode polysilicon layer in the core/peripheral circuit region remains to provide the same height between the cell array region where the cell capacitor is formed and the core/peripheral circuit region.

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Seoul, South Korea

Sang-Ho Song