Samsung Electronics Co., Ltd.

Sang-Ho An

In-Ku Kang

Sang-Sub Song

Dong-ok Kwak

Joon-young Oh

Tae-Gyeong Chung

Seok-chan Lee

Hye-jin Kim

Kyung-Man Kim

Sang-Yeop Lee

Ki-Hong Jeong

Hee-Kook Choi

Sun-Mo Yang

Sung-hoon Chun

Jeong-sik Yoo

Semiconductor packages including stacked semiconductor chips are provided. The semiconductor packages may include first semiconductor chips and a second semiconductor chip that are stacked sequentially on a board. The semiconductor packages may also include a wiring layer on the memory chips and the wiring layer may include redistribution patterns and redistribution pads. Each of the memory chips may include a data pad. The data pads of the first semiconductor chips may be electrically connected to the board via the second semiconductor chip, some of redistribution patterns, and some of redistribution pads.

Semiconductor package including stacked semiconductor chips and a redistribution layer

Provided is a semiconductor package including a plurality of first semiconductor chips that are stacked on a substrate and a second semiconductor chip disposed on the plurality of first semiconductor chips. The plurality of first semiconductor chips comprises a first semiconductor chip group and a second semiconductor chip group. The first semiconductor chip group is electrically connected to the second semiconductor chip through a first channel. The second semiconductor chip group is electrically connected to the second semiconductor chip through a second channel. At least one of the first channel and the second channel extends along a top surface of the first semiconductor chip which is disposed on the uppermost side, or top of the stack, among the plurality of first semiconductor chips. The inventive concept may provide the semiconductor package having a high operation speed, low power consumption, and a small thickness and capable of being manufactured at low costs.

Semiconductor package

Solid state drive (SSD) packages are provided including a controller package and at least one non-volatile memory package. The controller package and the at least one non-volatile memory package are connected to each other using a package-on-package (PoP) technique. A data input/output of the at least one non-volatile memory package is controlled by using the controller package.

Solid state drive packages and related methods and systems

A semiconductor device includes a substrate comprising a stack of alternating wiring layers and insulating layers. The wiring layers include conductive wiring patterns. Primary conductive vias extend through respective ones of the insulating layers and electrically connect first ones of the wiring patterns on different ones of the wiring layers to provide electrical connections between opposing first and second surfaces of the substrate. Dummy conductive vias extend through respective ones of the insulating layers and electrically connect second ones of the wiring patterns on different ones of the wiring layers. The dummy conductive vias are arranged in the substrate around a perimeter of a region including the first ones of the wiring patterns, and the dummy conductive vias and the second ones of the wiring patterns electrically connected thereto have a same electric potential to define an electromagnetic shielding structure within the substrate.

Substrates for semiconductor devices including internal shielding structures and semiconductor devices including the substrates

A method and apparatus for bonding a wire and a wire bond device formed by the same are disclosed. The method includes providing a carrier with at least a first pad, providing a semiconductor chip having at least the second pad, the at least second pad being smaller than the first a pad, forming a conductive stud bump on the second pad, and forming a bonding wire that has two terminal portions, which are respectively bonded to the first pad and the stud bump to electrically connect the first pad and the second pad. The stud bump is bonded to the second pad by a ball bonding method which uses a wire that has an approximately smaller diameter than the bonding wire. Further, a prominence formed on one end of the terminal portions is provided which has an approximately larger diameter than the stud bump.

Method and apparatus for bonding a wire

A multi-chip package and method for manufacturing are disclosed. The multi-chip package may include a substrate, a lower semiconductor chip mounted on the substrate, a first electrical connection for electrically connecting the substrate and the lower semiconductor chip, an upper semiconductor chip attached to the lower semiconductor chip and having overhang portions, and at least one bump interposed between the substrate and the overhang portions. The at least one bump may support the overhang portions and may be formed when the first electrical connection is formed.

Multi-chip package and method for manufacturing the same

Provided herein are multi-chip modules (MCMs) having bonding wires and fabrication methods thereof. The multi-chip module includes a substrate and a plurality of chips sequentially stacked. At least one top chip, stacked above a lowest chip, has an insulating film that covers the backside thereof. Also, each of the stacked chips has bonding pads formed on the periphery or edges of its upper surface. At least one insulator is interposed between the stacked chips. The insulator exposes the pads on the underlying chip. The pads of the respective chips are connected to a set of interconnections, which are disposed on the substrate. This configuration of stacked chips enables the overall height of the memory module to be reduced because the insulating film prevents the bonding wires from contacting the substrate of the top chips.

Growing community of inventors

Suwon-si, South Korea

Sang-Ho An