Hynix Semiconductor Inc.

Sang-Hee Kang

Hi-Hyun Han

Kyoung-Nam Kim

Ho-Youb Cho

Yong-Kyu Kim

Jun-Gi Choi

Sung-Joo Ha

A synchronous semiconductor memory device of the present invention includes: an operation controller for outputting a column active sense pulse in response to a column address and a column command signal; a shift register controller, activated in response to the column active sense pulse, for dividing a clock signal by N to thereby output a divided clock signal, N being a positive integer greater than 1; a plurality of shift registers connected in series and synchronized with the divided clock signal, wherein each shift register transmits the column active sense pulse to the next shift register; and a column active control signal generator for logically combining outputs of the shift registers to thereby generate a column active control signal.

Synchronous semiconductor memory device

A redundancy circuit in a semiconductor memory device comprises a fuse set controller configured to output a redundancy enable signal enabled according to applied address signals; a redundant selector; a spare redundant selector; and a spare fuse controller configured to be controlled by the redundancy enable signal, and to output a selection control signal that selects at least one of the redundant selector and the spare redundant selector in accordance with an internal fuse option.

Redundancy circuit semiconductor memory device

A semiconductor integrated circuit comprising: a first voltage generator configured to generate a first voltage in response to activation of a first enable signal, wherein the first enable signal is generated by detecting a level of the first voltage; and a second voltage generator configured to generate a second voltage in response to activation of at least one of the first enable signal and a second enable signal, wherein the second enable signal is generated by detecting a level of the second voltage.

Semiconductor integrated circuit and method of controlling internal voltage of the same

A semiconductor memory device prevents deterioration of refresh operation caused by sensing noise and a driving method thereof. First pull-down and second pull-down voltages which are different from each other are as a pull-down voltage of a bit line sense amplifier. The first and the second pull-down voltages are used in different driving periods to protect data from noises caused by another memory bank. A driving period can be separated into an initial sensing period, wherein large currents are consumed and significant noise is generated, and a subsequent stable period. The driving period can be separated into a pre-precharge period and a post-precharge period.

Semiconductor memory device and driving method thereof

A bit line over driving control signal generator generates an over driving control signal in response to an over driving signal. The over driving signal is generated in response to an active command. The bit line over driving control signal generator for use in a semiconductor memory device includes a delaying unit for delaying an over driving signal generated in response to an active command to thereby output a delayed over driving signal, a controlling unit for determining whether the delayed over driving signal is outputted without any modification or outputted with being disabled in response to the over driving signal, a read command, and a precharge command, and a pulse width adding unit for adding a predetermined pulse width of the delayed over driving signal to the over driving signal to thereby output a bit line over driving control signal.

Over driving control signal generator in semiconductor memory device

A semiconductor device for comparing an input address with a repair address includes a signal controller for generating control signals. An address latch unit in response to the control signals latches the address. Each of N number of M-bit address comparators compares the address with the stored repair address. A comparator delay modeling block delays the control signal for a predetermined time, i.e., delay value of the M-bit address comparator. A repair circuit controller in response to the delayed control signal output from the comparator delay modeling block generates one of a repair address enable signal and a normal address enable signal based on a comparison result of the M-bit address comparator.

Semiconductor memory device having advanced repair circuit

The present invention is related to a negative voltage generating circuit for reliably providing the semiconductor integrated circuit (IC) with a negative voltage. An electric charge pumping device generates a negative voltage by pumping an electric charge to a predetermined level supplied to one of a first node and a second node. A controlling device provides first and second pumping clock signal being clocked alternately every predetermined interval in response to a level of the negative voltage. A pumping controller controls an amount of electric charge supplied to the first node and the second node in response to the first and second pumping clock signals. Further, a reset controller resets the first node and the second node of the electric charge pumping means as the level of the negative voltage when the first and second pumping clock signals are inactivated.

Negative voltage generator circuit

Redundancy circuit in semiconductor memory device

A semiconductor memory device including a fuse control circuit for providing with a plurality of fail word line addresses written in its own circuit in advance and outputting a redundancy signal representing that an input address is the same as one of the fail word line addresses, and a normal word line interruption signal, a redundancy word line controller for inputting the redundancy signal and activating a designated redundancy word line; and a normal word line controller, for activating a word line corresponding to the input word line address, which is operated or interrupted in response to the normal word line interruption signal, wherein the normal word line interruption signal has a first logic state (logic low) at a pre-charge interval or when a same address as one of the fail word line addresses is inputted, and has a second logic state (logic high) when a normal address is inputted, and the redundancy signal has a first logic state (logic low) when a same address as one of the fail word line addresses is inputted, and a second logic state (logic high) at the pre-charge interval or when an address different from the fail word line addresses is inputted.

Redundancy fuse control circuit and semiconductor memory device having the same and redundancy process method

A semiconductor memory device, including: a plurality of banks each of which includes a plurality of memory cells, a plurality of redundancy memory cells for replacing a defective memory cell and a repair circuit, having a plurality of fuse sets, for substituting an address to thereby access the redundancy memory cell instead of the defective memory cell; and a common repair circuit, having a plurality of fuse sets, for substituting the address in order to replace the defective memory cell with the redundancy memory cell included in any of the plurality of banks.

Semiconductor memory device having repair circuit

A semiconductor memory device is capable of enhancing a sensing speed at a central region of a bit-line sense amplifier array by multiplying output lines of a sense amplifier driver. For the purpose, the semiconductor memory device includes a sense amplifier array unit including a plurality of bit-line sense amplifiers arrayed to each other, a first driver, located at one side of the sense amplifier array unit, for generating a driving voltage of the plurality of bit-line sense amplifiers, a second driver, located at the other side of the sense amplifier array unit, for producing the driving voltage of the plurality of bit-line sense amplifiers, a first power line, which is connected between an output node of the first driver and that of the second driver, and to which a driving voltage input node of each of the plurality of bit-line sense amplifiers is attached in parallel, and a second power line, connected to the first power line in parallel between the output node of the first driver and that of the second driver, and strapped with the first power line at least one point.

Growing community of inventors

Ichon-shi, South Korea

Sang-Hee Kang