Hyundai Electronics Industries Co. Ltd.

Hyundai Electronics Industries

Sang H Woo

Ha E Jeon

Il Keoun Han

Young Jin Park

Hong Seon Yang

Seung Woo Shin

Hoon Jung Oh

Jong Cheol Kim

Seong Su Lim

Kwang Seok Jeon

Jung Yun Mun

The present invention relates to semiconductor manufacturing field, more particularly, to a process of forming a charge storage electrode to which a selective hemispherical grains (HSG) silicon film is applied. The object of the present invention is to provide a method of forming a charge storage electrode having the selective HSG silicon film in semiconductor device which can secure a sufficient capacitor effective surface area by obtaining desired grain size at the time of selective HSG silicon film formation. The present invention prevents remaining of carbon component which obstructs the growth of HSG silicon film after dry etching process by limiting the carbon halide gas used in dry etching process of amorphous silicon film for defining the charge storage electrode at the time of process of forming the charge storage electrode having selective HSG silicon film. That is, the present invention is a technology of etching a part of amorphous silicon film by using general carbon halide gas at the time of dry etching process of the amorphous silicon film for defining the charge storage electrode, and then, finally etching the remaining part of amorphous silicon film by using silicon etching gas such as SF,gas, Cl,&plus;O,gas, HBr gas, etc. not containing carbon component or only using the etching gas such as SF,gas, Cl,&plus;O,gas, HBr gas, etc. not containing carbon component during selective etching of amorphous silicon film.

Method of forming a charge storage electrode having a selective hemispherical grains silicon film in a semiconductor device

The present invention is a method which can obtain an actual value close to a desired capacitance of capacitor by precisely monitoring the area variation rate of film by using a correlation between a height of hemispherical grains formed on a surface of film and a surface area of film. The present invention provides a method of calculating an area variation rate `C.sub.E ` by using the porosity ratio `f.sub.v ` and the height `t` of hemispherical grains and measuring the capacitance of capacitor by using the obtained area variation rate. According to this method, the area variation rate of film can be obtained close to actual value by measuring the height of hemispherical grains formed on the surface of film, and the variation in capacitance before completion of capacitor can be precisely obtained. In addition, the present invention has effects of improving the reliability and manufacturing yield of capacitor by enabling the monitoring of area variation rate close to actual value in the step of forming the hemispherical grains on the surface of film.

Method of measuring surface area variation rate of a polysilicon film

This invention discloses a method of forming an electrode of semiconductor device. In the present invention, an amorphous silicon film is formed on a substrate, and silicon seeds are formed on the silicon film. Thereinafter, the heat treatment is performed for growing, thereby forming an hemispherical roughness structure on surface of said charge storage electrode and increasing a surface area in unit area.

Method of forming an electrode of a semiconductor device

A method for fabricating a storage electrode of a semiconductor device, capable of forming the storage electrode to have a rough surface with hemispherical lugs by use of simplified deposition process and heat treatment using a single process tube to obtain a high capacitance in spite of a small cell area, thereby greatly improving the operation characteristic of the semiconductor device. The method includes the steps of bring a doped amorphous silicon film into contact with a portion of a substrate to be contact with the storage electrode, repeatedly forming an undoped amorphous silicon film and another doped amorphous silicon film over the doped amorphous silicon film at least one time, subjecting all the doped and undoped amorphous silicon films to a thermal treatment in an inert gas atmosphere for a time so that a dopant of each doped amorphous silicon film is diffused in a portion of the undoped amorphous silicon film while all the doped and undoped amorphus silicon films are crystallized into polysilicon films respectively; and etching the polysilicon films by use of a wet etch solution exhibiting an etch selectivity to an undoped one of the polysilicon film so that doped ones of the polysilicon films are etched at a higher rate than the undoped polysilicon film.

Method for fabricating storage electrode of semiconductor device

A storage electrode of a DRAM cell in a highly-integrated semiconductor device has, in order to secure the surface area thereof greater than that of a conventional tunnel-type storage electrode, an upper plate of storage electrode formed over a lower plate of storage electrode separated therefrom by a predetermined distance, while interposing bars of irregularly shapes formed of a conductive layer to electrically connect the upper and lower plates.

Storage electrode of DRAM cell

There is disclosed a method for the fabrication of a capacitor of a DRAM, comprising the characteristic steps of: forming a bellows type storage electrode; depositing an impurity-doped polysilicon film on the entire surface of the storage electrode; and diffusing the dopants into impurity-rare edge portions of the storage electrode through an annealing treatment. Accordingly, it is capable of easily securing the capacitance of a capacitor in greater quantity per unit area, and thus, effects a reduction in production cost.

Method for fabricating stacked capacitor of a DRAM cell

A method is disclosed for the wet etching of polysilicon, which comprises the steps of: annealing a lamination structure of a doped polysilicon and an undoped polysilicon at a predetermined temperature for a predetermined period; and applying to the annealed lamination structure a chemical etchant comprising nitric acid, fluoric acid, acetic acid and deionized water with the volume ratio of nitric acid to acetic acid to fluoric acid to deionized water being 30:3:x:15+(1-x) wherein x is a real number ranging from 0.2 to 1.0, so as to remove the doped polysilicon film. Instead of fluoric acid, alcohol may be used in the chemical etchant without affecting the etching selectivity. This method is superior in performance with regard to selective etching between the undoped polysilicon and the doped polysilicon. Therefore, the doped polysilicon which is useful in many ways, for example, storage electrode, insertion layer and contact, can be etched in such a thickness as is needed, with the chemical etchant. Consequently, the present method is very useful in developing new semiconductor devices.

Method for wet etching polysilicon

A method for fabricating a storage electrode of a DRAM cell capable of preventing impurities from excessively moving from the storage electrode to diffusion regions. The storage electrode is formed by a double formation of polysilicon layers. An undoped polysilicon layer 11 is primarily deposited over the entire exposed surface of the resulting structure to a thickness corresponding to 40 to 50% of a predetermined thickness of the storage electrode. A doped polysilicon layer is secondarily deposited over the undoped polysilicon layer to a thickness corresponding to 60 to 50% of the predetermined thickness of the storage electrode. The doped polysilicon layer and the undoped polysilicon layer are subjected to a patterning so that predetermined portions thereof are removed so as to form the storage electrode.

Method for fabricating storage electrode of dynamic random access memory

A method is disclosed for forming a gate electrode having two polysilicon layers and a tungsten silicide layer to prevent fluorine gas diffusion along grain boundaries from penetrating into a gate oxide film. This method for forming a gate electrode is comprised of sequentially forming a gate oxide film and a first polysilicon layer on a silicon substrate, enlarging the grain size of the first polysilicon layer by heat treatment, introducing a reagent gas, either SiH.sub.4 or Si.sub.2 H.sub.6, to further adjust the grain size within said layer, forming a second polysilicon layer on the first polysilicon layer, enlarging the grain size of the second polysilicon layer by heat treatment, introducing a reagent gas, either Si.sub.2 H.sub.6 or SiH.sub.4, whichever one was not used to treat the first polysilicon layer, forming a tungsten silicide layer on the second polysilicon layer, and patterning the tungsten silicide layer, the second polysilicon layer and the first polysilicon layer by means of a mask etching process.

Method for forming a two-layered polysilicon gate electrode in a

A method for manufacturing a TFT of a SRAM in a highly-integrated semiconductor device, to enlarge the grain size of a polysilicon film, includes steps of depositing amorphous silicon film under a pressure capable of maintaining a uniform thickness thereof, and forming a polysilicon film which has a maximized grain size in the same tube that the amorphous silicon film has been deposited, while performing an annealing process by raising the temperature to 600.degree.-650.degree. C. for 4-10 hours under the pressure which is lowered to approximately 10.sup.-3 Torr. The polysilicon film having a maximized grain size is utilized as the channels of the TFT.

Method for manufacturing a thin film transistor

A method for manufacturing a conductor layer in a semiconductor device is achieved with a reduced resistivity in the conductor layer. When a polycide film comprised of a polysilicon film and a tungsten silicide film is manufactured, the grain size of the polysilicon film is increased to reduce the resistivity of the polysilicon film. Also, the silicon in the tungsten silicide film is transferred to the boundary between the tungsten silicide film and the polysilicon film to increase the adhesion properties therebetween. Accordingly, a lifting or separation phenomenon is eliminated. Furthermore, since the silicon in the tungsten silicide film is decreased by the transfer, the resistance of the conductor layer is reduced.

Method for manufacturing a conductor layer in a semiconductor device

A storage electrode of a DRAM cell in a highly-integrated semiconductor device has, in order to secure the surface area thereof greater than that of a conventional tunnel-type storage electrode, an upper plate of storage electrode formed over a lower plate of storage electrode separated therefrom by a predetermined distance, while interposing bars of various shapes formed of a conductive layer to electrically connect the upper and lower plates, and a method for manufacturing the storage electrode is also provided.

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Kyoungki-do, South Korea

Sang H Woo