Electronics and Telecommunications Research Institute

Sang Gi Kim

Jin Gun Koo

Yil Suk Yang

Seong Wook Yoo

Gyungock Kim

Jong Dae Kim

Dae Woo Lee

Tae Moon Roh

Ki Seok Jang

In Gyoo Kim

Sang Hoon Kim

Jiho Joo

Jaegyu Park

Jongdae Kim

Yongseok Choi

Sahnggi Park

Yong Sun Yoon

Hyuk Je Kwon

Hyundai Park

Jong Moon Park

Sun Ae Kim

Jin Hyuk Oh

Myung Joon Kwack

Jin-Gun Koo

Byung Won Lim

Yoon Kyu Bae

Jin Ho Lee

Bo Woo Kim

Il Yong Park

Kun Sik Park

Kee Soo Nam

Jong-Moon Park

Kyoung Il Na

Jeong Woo Park

Jimin Oh

Junghyung Pyo

Sanghoon Kim

Duk Jun Kim

Hyun-cheol Bae

Sewan Heo

Byoung-Gon Yu

Dongwoo Suh

JiHo Joo

MinKi Kim

Do Won Kim

Kap-Joong Kim

Dae Seo Park

Jongbum You

Jong Il Won

Il-yong Park

Roh Tae Moon

Yang Yil Suk

II-Young Park

Ju Wook Lee

Boo Woo Kim

Kun Sik Pakr

Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.

Opto-electronic system including optical input/output device

Method of manufacturing optical input/output device

An optical device module includes a substrate, an interlayer insulating layer on the substrate, an optical waveguide on the interlayer insulating layer, an optical device on the optical waveguide, and a prism disposed between the optical device and the optical waveguide. The prism has a refractive index greater than a refractive index of the optical waveguide.

Optical device module and optical communication network system using the same

Optical input/output device, optical electronic system including the same, and method of manufacturing the same

Provided is a semiconductor device. The semiconductor device includes: a first semiconductor layer having a first region with a first device and a second region with a second device; a device isolation pattern provided in the first semiconductor layer and electrically separating the first device and the second device from each other; a drain provided on a lower surface of the first region of the first semiconductor layer; and a second semiconductor layer provided on a lower surface of the second region of the first semiconductor layer.

Semiconductor device and method of fabricating the same

Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.

Disclosed is a power supply module for a hall sensorless BLDC motor, including: a high-voltage/large-current power device t applied with high voltage/large current and including a plurality of power devices driving the hall sensorless brushless direct current (BLDC) motor; a motor driving circuit sensing and controlling a positional signal or a velocity signal of the hall sensorless BLDC motor and generating a PWM control signal for controlling the hall sensorless BLDC motor; and a power device driving circuit driving the high-voltage/large-current power device according to the PWM control signal of the motor driving circuit, wherein the high-voltage/large-current power device, the power device driving circuit, and the motor driving circuit are CMOS-integrated on the same substrate.

Power supply module for hall sensorless brushless direct current motor

Provided is an electro-optic modulating device. The electro-optic modulating device includes an optical waveguide with a vertical structure and sidewalls of the vertical structure are used to configure a junction.

Electro-optic modulating device

Provided is a wafer exposure apparatus used in a semiconductor device manufacturing process, the exposure apparatus including: a reflective mirror for reflecting light provided from a light source; an optical path changer for changing a path of the light provided from the reflective mirror; first mirrors installed at both sides of the optical path changer to change the path of the light; second mirrors installed at both sides of a material to change the path of the light; and third mirrors installed at both sides of a mask to enter the light reflected by the first mirrors to the mask and to enter the light passed through the mask into the second mirrors, whereby it is possible to continuously expose one surface, both surfaces or a specific surface of a wafer in a state that the wafer is once aligned.

Exposure apparatus

Provided is a photodetector in which a transparent nonconductive material having an interface charge and a trapped charge is deposited on a semiconductor surface so as to form a depletion region on the surface of the semiconductor, and the depletion region is employed as an optical detecting region, thereby not only improving detection with respect to light having a wavelength of ultraviolet and blue ranges but also filtering light having a wavelength of visible and infrared ranges, and in which a fabricating process thereof is compatible with a universal silicon CMOS process.

Semiconductor photodetector for detecting light having a wavelength in the ultraviolet blue ranges

Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible to readily perform a compound semiconductor device manufacturing process, and to reduce manufacturing cost by means of the increase of manufacturing yield and the simplification of manufacturing processes.

Method of fabricating T-type gate

The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.

Method for fabricating a high-voltage high-power integrated circuit device

A method for fabricating a power semiconductor device having a trench gate structure is provided. An epitaxial layer of a first conductivity type having a low concentration and a body region of a second conductivity type are sequentially formed on a semiconductor substrate of the first conductivity type having a high concentration. An oxide layer pattern is formed on the body region. A first trench is formed using the oxide layer pattern as an etching mask to perforate a predetermined portion of the body region having a first thickness. A body contact region of the second conductivity type having a high concentration is formed to surround the first trench by impurity ion implantation using the oxide layer pattern as an ion implantation mask. First spacer layers are formed to cover the sidewalls of the first trench and the sidewalls of the oxide layer pattern. A second trench is formed using the oxide layer pattern and the first spacer layers as etching masks to perforate a predetermined portion of the body region having a second thickness greater than the first thickness. A source region of the first conductivity type having a high concentration is formed to surround the second trench by impurity ion implantation using the oxide layer pattern and the first spacer layers as ion implantation masks. Second spacer layers are formed to cover the sidewalls of the second trench and the sidewalls of the first spacer layers. A third trench is formed to a predetermined depth of the epitaxial layer using the oxide layer pattern, the first spacer layers, and the second spacer layers as etching masks. A gate insulating layer is formed in the third trench. A gate conductive pattern is formed in the gate insulating layer. An oxide layer is formed on the gate conductive layer pattern. The first and second spacer layers are removed. A first metal electrode layer is formed to be electrically connected to the source region and the body contact region. A second metal electrode layer is formed to be electrically connected to the gate conductive layer pattern. A third metal electrode layer is formed to be electrically connected to the semiconductor substrate.

Method for fabricating power semiconductor device having trench gate structure

Growing community of inventors

Daejeon, South Korea

Sang Gi Kim