Samsung Electronics Co., Ltd.

Sang-Eun Lee

Yun-Heub Song

Jin-Ho Kim

Joon-Young Choi

Sam-jong Choi

Jae-Sung Han

Bong-Yong Lee

Tae-Hyun Yoon

Kyung-Jun Shin

Hae-Bum Lee

Jung-Ro Ahn

Jung-In Han

Ju-Seong Hwang

Young-Chol Lee

A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density. In some embodiments, the first plane index may be (100) and the second plane index may be (100) or (310).

Nonvolatile memory devices with aligned trench isolation regions

In a non-volatile memory system, a plurality of main memory cells for storing data is arranged in a data cell array and a plurality of reference memory cells is arranged in a reference cell array. The reference cell array includes first reference word lines connected to first reference memory cells and extending, second reference word lines connected to second reference memory cells and extending alternately with the first reference word lines, reference bit lines to which the first and the second reference memory cells are alternately connected in a line and a combined cell having a pair of the first and second reference memory cells and generating a reference signal for processing the data. The first and the second reference memory cells have different cell characteristics. The stability of the reference signal is improved irrespective of the differentiation of the first and the second reference memory cells.

Non-volatile memory systems having at least one pair of memory cells

Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.

Method of manufacturing a semiconductor integrated circuit using a selective disposal spacer technique and semiconductor integrated circuit manufactured thereby

Method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit manufactured thereby

Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions between the gate patterns include first spaces having a first width and second spaces having a second width greater than the first width. Spacers are formed on sidewalls of the second spaces, and spacer layer patterns filling the first spaces are also formed together with the spacers. The spacers are selectively removed to expose the sidewalls of the first spaces. As a result, the semiconductor integrated circuit includes wide spaces enlarged by the removal of the spacers and narrow and deep spaces filled with the spacer layer patterns.

Semiconductor integrated circuit using a selective disposable spacer

According to a preferred aspect of this invention, locations of defects on a semiconductor wafer are found using semiconductor defect inspection instrumentation. Defect composition can also be determined using inspection instrumentation. Wafer defects are represented on a wafer defect map using markings wherein locations of the markings on the map correspond to the locations of the defects on the wafer. The markings also preferably represent a defect type and/or composition. Color-coded dots, for instance, can be used to represent like defect causes or types with like colors. Graphs can be prepared to display defect characteristics using distributions and skews to facilitate quick statistical analysis of the defects. In this manner, wafer defects can be analyzed quickly and efficiently based on characteristics thereof, including, for example, defect type, composition, and cause. This information can be used to help prevent future defects during mass production, thereby improving yield.

Method of identifying and analyzing semiconductor chip defects

An apparatus rotates a sample to facilitate an accurate analysis of the sample. The apparatus includes a sample stage on which a plurality of samples are supported, a rotatable cap and a linearly movable plate for placing a selected one of the samples at an analysis position, and a rotating stage that supports the sample stage, rotatable cap and movable plate. The rotating stage is rotatable about an axis of rotation that intersects the analysis position. Once the selected sample is placed at the analysis position by the rotation of the cap and the linear movement of the plate, the selected sample is rotated by the rotating stage. The analysis process can be selectively or sequentially carried out with respect to the plurality of samples with a high degree of efficiency and without the associated drive mechanisms experiencing high loads.

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Gyeonggi-do, South Korea

Sang-Eun Lee