Hynix Semiconductor Inc.

Sang-Don Lee

Jin-Hong Ahn

Yil-Wook Kim

Sang-Hoon Hong

Young-June Park

Gi-Hyun Bae

Hee-Bok Kang

Young-Jun Park

A semiconductor memory device includes a first cell array including a plurality of unit cells and a bit line sense amplifying unit for sensing and amplifying data signals stored in the unit cells. Each unit cell is provided with a PMOS transistor and a capacitor. Therefore, the semiconductor memory device efficiently operates with low voltage without any degradation of operation speed.

Semiconductor memory device for low voltage

The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

Transistor of volatile memory device with gate dielectric structure capable of trapping charges

A unit cell included in a non-volatile dynamic random access memory (NVDRAM) includes a control gate layer coupled to a word line; a capacitor for storing data; a floating transistor for transmitting stored data in the capacitor to a bit line, gate of the floating transistor being a single layer and serving as a temporary data storage; and a first insulating layer between the control gate layer and the gate of the floating transistor, wherein a voltage supplied to body of the floating transistor is controllable.

Apparatus and method of driving non-volatile DRAM

A method for operating a non-volatile dynamic random access memory (NVDRAM) device having a plurality of memory cells, each cell having a capacitor and a transistor having a floating gate includes the steps of (A) preparing a power-on mode for performing a DRAM operation; and (B) preparing a power-off mode for holding stored data in the memory cell.

Non-volatile dynamic random access memory

A driving circuit for use in a non-volatile dynamic random access memory (NVDRAM) having a nonconductor which can trap electrons or holes includes an internal supply voltage generator for generating the plurality of internal supply voltages, each having at least two different voltage levels; a mode controller for determining an operation mode of the NVDRAM; a voltage level selector for selecting one voltage level of each internal supply voltage in response to the operation mode to thereby outputs the selected voltage level of each internal supply voltage to the row decoding block and the core area; a row decoding block for receiving the internal supply voltages and outputting the internal supply voltages in response to an inputted address; and a core area having a plurality of unit cells, each storing a data, for accessing the data in response to inputted voltage levels of the plurality of internal supply voltages.

Driving circuit for non-volatile DRAM

The present invention relates to a method for fabricating a metal-oxide semiconductor (MOS) transistor having a gate electrode with a stack structure of a polysilicon layer, a tungsten nitride barrier layer and a tungsten layer. According to the present invention, a depth from a lastly deposited nitride layer to a bottom surface of a trench is shallower, and thereby decreasing incidences of a void generation. Also, the present invention provides an advantage of an elaborate manipulation of well and channel dopings by performing ion-implantations with two different approaches. Furthermore, it is possible to enhance device characteristics by decreasing gate induced drain leakage (GIDL) currents and improving a capability of driving currents. This decrease of the GIDL currents and the improved driving current capability are obtained by forming the gate oxide layer with different thicknesses.

Growing community of inventors

Ichon-shi, South Korea

Sang-Don Lee