Samsung Electronics Co., Ltd.

Sang-Chul Kang

Jin-Yub Lee

Gwang-Man Lim

Seok-Jae Han

Il-Mok Kang

Seok-Cheon Kwon

Yong-Taek Jeong

Hyung-Min Kim

Seok-Chan Lee

Ho-kil Lee

Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.

Multi-bit flash memory devices having a single latch structure and related programming methods, systems and memory cards

Methods of executing a multi-page copyback program in a non-volatile memory device are provided, where the non-volatile memory device includes a memory having a plurality of memory blocks. A page of data of the memory block having a first address is replaced responsive to a generated multi-page copyback program command. It is determined if the first address of the page of data is the same as a stored address of the page at which the failure was detected. The first address is incremented if it is determined that the first address and the stored address are not the same. The pages of data are replaced, the addressed are compared and the addresses are incremented until it is determined that the incremented address and the stored address are the same. Related devices and systems are also provided herein.

Flash memory devices having multi-page copyback functionality and related block replacement methods

A semiconductor device includes a memory cell array and a command interface that is configured to receive a command from outside of the semiconductor memory device. The command interface is further configured to interpret the received command and to determine if the received command is a continuous operation command. The command interface outputs a command signal corresponding to the command and at least one flag signal that indicates a continuous operation section if the command is a continuous operation command. A control unit is configured to receive the command signal and the at least one flag signal output from the command interface, and to generate a pump control signal based on the received command signal and the at least one flag signal. A charge pump is configured to generate a voltage in response to the pump control signal for use in accessing the memory cell array to read write and/or erase data.

Semiconductor memory devices having control circuitry to avoid recovering a charge pump when executing consecutive sections of a continuous operation command and methods of operating the same

A non-volatile memory device capable of improving a read characteristic includes memory blocks, each memory block having a plurality of word lines. A common source line is arranged to be shared by the memory blocks. A first transistor is connected to the common source line, and a voltage higher than a power supply voltage is applied to a gate of the first transistor during a read operation. A second transistor connects the first transistor to a reference voltage during the read operation.

Nonvolatile memory device controlling common source line for improving read characteristic

Semiconductor memory devices include a memory array having a plurality of multi-column memory blocks therein and a multi-column redundant memory block. A redundancy column selecting unit is provided, which is configured to route data read from the multi-column redundant memory block to a redundant data line, in response to a column address. A data input/output unit is also provided. This data input/output unit is connected to the redundant data line and a data line associated with a defective column in the memory array. The data input/output unit is configured to respond to an instruction to read first data from a defective column in the memory array by routing first data read from a selected redundant column in the multi-column redundant memory block to an input/output bus while concurrently blocking data read from the defective column from being transferred to the input/output bus.

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Gyeonggi-do, South Korea

Sang-Chul Kang