Samsung Electronics Co., Ltd.

Sang-chul Kang

Gwang-Man Lim

Seok-Jae Han

Il-Mok Kang

Seok-cheon Kwon

Seok-chan Lee

Eun-Jin Yun

Jin-Yub Lee

Seung-Jae Lee

Hyung-Min Kim

Yong-Taek Jeong

Kyong-Ae Kim

Provided is a memory card, which includes two pairs of opposite edges, first row terminals arranged adjacent to an insertion-side edge of the memory card, and second row terminals arranged apart from the insertion-side edge of the memory card. The memory card can be easily reset in terms of software without controlling power supply in terms of hardware. Also, the memory card can be smoothly attached and detached during insertion of the memory card into a socket and reduce damage to a device.

Memory card having multi-row terminals

A nonvolatile memory device comprises a memory cell array and a voltage generator. The memory cell array comprises a plurality of memory cells connected in series between a string selection transistor connected to a bit line and a ground selection transistor connected to a source line. The voltage generator provides read voltages to word lines of memory cells selected from among the plurality of memory cells during a read operation. The read voltages of the selected memory cells differ from each other according to their respective distances from the string selection transistor.

Non-volatile memory device and related read method using adjustable bit line connection signal

Memory card

Non-volatile memory device and related read method

A nonvolatile memory device comprises a memory cell array, a page buffer, and a bit line connection signal controller. The memory cell array comprises a plurality of word lines and bit lines arranged in rows and columns, and a plurality of memory cells connected to the respective word lines and bit lines. The page buffer connects a selected bit line among the plurality of bit lines to the page buffer, applies a precharge voltage to the selected bit line, and senses a voltage of the selected bit line after developing of the selected bit line according to a bit line connection signal, during a read operation. The bit line connection signal controller changes the bit line connection signal according to a control signal, during the read operation.

According to an example embodiment, a method of changing a block size in a flash memory device having a multi-plane scheme may include decoding an external input address and changing the block size of the flash memory device from a first block size to a second block size. The external input address may be decoded into a block address and a page address. The block size of the flash memory device may be changed from the first block size to the second block size by shifting at least one bit of the block address to the page address or shifting at least one bit of the page address to the block address.

Flash memory device and method of changing block size in the same using address shifting

A flash memory device capable of efficiently determining whether most significant bit (MSB) programming has been performed is provided. The flash memory device includes a cell array, a control unit, and a determination unit. The cell array includes at least one flag cell for storing information about whether MSB programming has been performed on a multi-level cell. The control unit controls a program operation, a read operation, and an erasure operation with respect to the cell array. The determination unit receives flag data stored in the flag cells, performs an OR operation and/or an AND operation on the flag data, and generates a determination signal based on a result of the OR operation and/or the AND operation, wherein the determination signal represents whether the MSB programming has been performed.

Flash memory device for determining most significant bit program

The present invention is directed to a dual chip package that is connected to a host and includes a first memory chip and a second memory chip. Each of the first and second memory chips includes a flash memory; an option pad connected to either a first or second voltage; a register configured to store a flag signal indicating whether a memory chip is selected; a comparator circuit configured to compare a flag signal stored in the register with a logic value apparent at the option pad to generate a flash access signal. Each of the first and second memory chips also includes a memory controller unit configured to access the flash memory in response to the flash access signal, and an interrupt controller unit configured to provide an interrupt signal to the host in response to the flash access signal and a control signal provided from the host.

Growing community of inventors

Hwaseong-si, South Korea

Sang-chul Kang