Samsung Electronics Co., Ltd.

Sang-cheol Han

Mi-young Kim

Kyoung-woo Lee

Hong-Seong Son

Ja-Eung Koo

Jun-Hwan Oh

Duk-Ho Hong

Moo-yong Park

Jeong-Wook Hwang

Tai-hyoung Kim

A method of forming a dual damascene semiconductor interconnection and an etchant composition specially adapted for stripping a sacrificial layer in a dual damascene fabrication process without profile damage to a dual damascene pattern are provided. The method includes sequentially forming a first etch stop layer, a first intermetal dielectric, a second intermetal dielectric, and a capping layer on a surface of a semiconductor substrate on which a lower metal wiring is formed; etching the first intermetal dielectric, the second intermetal dielectric, and the capping layer to form a via; forming a sacrificial layer within the via; etching the sacrificial layer, the second intermetal dielectric, and the capping layer to form a trench; removing the sacrificial layer remaining around the via using an etchant composition including NHF, HF, HO and a surfactant; and forming an upper metal wiring within the thus formed dual damascene pattern including the via and the trench. The preferred etchant composition for stripping a sacrificial layer in the foregoing dual damascene process consists essentially of NHF, HF, HO and a surfactant.

Method of fabricating dual damascene interconnection and etchant for stripping sacrificial layer

Methods are provided for fabricating a semiconductor device that include the steps of: sequentially forming a metal interconnection and a protecting layer on a semiconductor substrate; forming a contact hole on the protecting layer; isolating the contact hole by forming a molding layer and an etching stop layer stacked thereon; forming a sacrificial layer on the etching stop layer so as to fill the contact hole; forming a photoresist layer with an opening so as to expose the sacrificial layer and such that the opening of the photoresist layer aligns with the contact hole; forming a trench in the molding layer to penetrate the sacrificial layer and the etching stop layer; and performing a wet etching on the semiconductor substrate having the trench to remove the photoresist layer and the sacrificial layer, wherein the wet etching step is performed using an organic compound and fluoride ion-based buffered solution.

Methods of fabricating a semiconductor device using an organic compound and fluoride-based buffered solution

Methods of fabricating a microelectronic device having improved performance characteristics are disclosed which are characterized by using super critical fluid to perform a material removal step. In one illustrative embodiment, the method includes preparing a substrate, forming an HSQ layer covering at least a portion of the substrate, and thereafter removing at least portions of the HSQ layer using super critical fluid CO.

Method of fabricating microelectronic device using super critical fluid

A flexible membrane for a polishing head and a chemical mechanical polishing (CMP) apparatus having the same are provided. The flexible membrane for a polishing head includes a compressing plate having a first face and a second face opposite to the first face. The first face of the compressing plate holds a substrate with a vacuum provided thereto and compresses the substrate on a polishing pad. The second face of the compressing plate is combined with a supporter of the polishing head. The second face and the supporter define a space to which the vacuum for holding the substrate and a first pneumatic pressure for compressing the substrate are applied. A dividing member combined with the supporter is formed on the second face. The dividing member divides the space into at least two regions. A pneumatic pressure-introducing portion is formed at the dividing member. A second pneumatic pressure is provided to the compressing plate through the pneumatic pressure-introducing portion.

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Seoul, South Korea

Sang-cheol Han