Samsung Electronics Co., Ltd.

Water Resources Engineering Corporation

Robogen Co., Ltd.

Sang-bong Park

Sang-tae Kim

Jun-kyoung Lee

Jong-hak Won

Dong-Sung Joo

Mun-Suk Chun

Hyuk-Sung Park

Hae-Sung Park

Kyeong-Soo Min

Jae-Yeon Ryu

Kyeong-Sub Lee

Sung-Joon Ko

Jeong-gyun Yu

Dong-Hyun Kim

A multi-subscriber identification module (SIM) device is provided. The multi-SIM device includes a first SIM interface; a second SIM interface; and at least one processor configured to implement: a base station (BS) searcher configured to perform a resynchronization operation for securing synchronization with a BS or a measurement operation for measuring signal quality of the BS based on a request received from the first SIM interface; and a searcher scheduler configured to receive the request for use of the BS searcher from the first SIM interface, and identify whether the first SIM interface is granted use of the BS searcher based on the request and a schedule for the BS searcher.

Multi-SIM device for performing scheduling for base station searcher and method of scheduling base station search

An apparatus for photographing a pipe without suspension of water supply and a system for controlling the same are disclosed. According to present invention, the interior of the pipe can be photographed by inserting the camera into the pipe and moving and rotating the camera without halting water supply, and information about the movement and rotation of the camera can be produced. A problem of discontinuance of using the whole pipe due to photographing of the interior of the pipe can be prevented. The camera can accurately photograph respective portions in the pipe by precisely moving forward/backward and rotating left/right or up/down. Since information about a practical position in the pipe with respect to the photographed image is provided, a user can accurately grasp a defect-position in the pipe, and can easily control the camera.

Apparatus for photographing pipe without suspension of water supply and system for controlling the same

A memory test control circuit in an MML integrated circuit is connected to a first pad which receives memory control signals to control first and second memories of the MML circuit. The memory test control circuit is also connected to a second pad which receives memory data signals for the first and second memories. The memory test control circuit is also connected to the logic block and to the first and second memories. The memory test control circuit transmits the memory control signals and the memory data signals to the first and second memories when the first and second memories are tested and transmits the memory control signals and the memory data signals to the logic block during normal operation of the MML integrated circuit. Accordingly, the memory test control circuit allows pass-through of memory data and control signals directly to the memory blocks during test mode, and provides the memory data and control signals to the logic block during normal operations.

Merged memory and logic (MML) integrated circuits including memory test controlling circuits and methods

Integrated circuit memory devices having self test circuits therein may be tested by performing an interleave test on a plurality of memory banks in the memory device, to determine a first test failure and then performing a bank-by-bank test on the plurality of memory banks with all of a plurality of AC parameters set to respective minimum margin conditions, to determine a second test failure. These AC parameters may include a first bank active to first bank active time interval (tRC), a first bank active to first bank read time interval (tRCD), a first bank active to first bank precharge time interval (tRAS), a first bank precharge to first bank active time interval (tRP) and a column address to column address delay time interval (tCCD). A bank-by-bank test is then performed on the plurality of memory banks with all of the plurality of AC parameters set to respective maximum margin conditions, to determine a third test failure. Finally, a bank-by-bank test is performed on the plurality of memory banks with only one of the plurality of AC parameters set to a respective minimum margin condition. This latter step is repeated for each AC parameter and need not be performed unless the first and second test failures occur and the third test failure does not occur.

Integrated circuit memory devices having self-test circuits therein and

Growing community of inventors

Yongin-si, South Korea

Sang-bong Park