Samsung Electronics Co., Ltd.

Sang-Bom Kang

Gil-heyun Choi

Seong-Geon Park

Sang-Woo Lee

Yu-Gyun Shin

Hyun-Su Kim

Hye-Lan Lee

Taek-Soo Jeon

You-Kyoung Lee

Kwang-Jin Moon

Kyung-In Choi

Jong-Myeong Lee

Chul-Sung Kim

Hyun-seok Lim

Hag-Ju Cho

In-sang Jeon

Seung-Jae Lee

Myeong-Cheol Kim

Sang-in Lee

Sang-Jin Hyun

Byeong-Chan Lee

Dae-Yong Kim

Hong-bae Park

Jong-Ho Yun

Woong-Hee Sohn

In-Sang Jeon

Hyo-Seok Choi

Jeong-Ik Kim

Jung-Chan Lee

Seung-Gil Yang

Yun-sook Chae

Chung-Hwan Shin

Je-Hyung Ryu

Chang-soo Park

Cheol Kyu Kim

June-Hee Lee

Hee-Sook Park

Yong-Ho Jeon

Seung-Hun Lee

Hyun-jung Lee

Seok-Hoon Kim

Wook-Je Kim

Gil-Heyun Choi

Hag-ju Cho

Tae-Ouk Kwon

Chung-Geun Koh

Dae-young Kwak

Kwan-Yong Lim

Yung-sook Chae

Bo-un Yoon

Byung-Hee Kim

Si-Young Choi

Jin-Ho Park

In-gyu Baek

Dong-Chan Kim

Hee-Soo Kang

Hyun-Jo Kim

In-Sun Park

Ki-Hong Kim

Yong-Ho Ha

Eun-Ji Jung

Hoon-Joo Na

Jae-yup Chung

Beom-jun Jin

Sang-Yong Kim

Kwan-heum Lee

Gab-Jin Nam

Sug-Woo Jung

Soo-Hun Hong

Jeong-Hee Han

Hyun-Jun Sim

Sang-In Lee

Sun-ghil Lee

Jong-Seo Hong

Jae-Jung Kim

Sug-hun Hong

Jae-Yeol Song

Hyeok-Jun Son

Hyung-Seok Hong

Hee-Don Jeong

Ki-Hyung Ko

Sug-Hun Hong

Sang-jin Hyun

Ui-hui Kwon

Jae-young Park

Dae-Young Kwak

Woo-bin Song

Yoo-Jung Lee

Moon-Kyu Park

Kang-Hun Moon

Soon-Wook Jung

Jae-Sung Hur

Yun-Sook Chae

Han-ki Lee

Hyun-seung Kim

Young-Su Chung

Heung-Kyu Park

Kyu-wan Ryu

Hyun-Deok Yang

Sang-Mi Choi

A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

Methods of fabricating semiconductor devices using MOS transistors with nonuniform gate electrode structures

A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

Semiconductor devices with shaped portions of elevated source/drain regions

A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.

Semiconductor device

Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.

Methods of fabricating semiconductor devices

Methods of forming semiconductor devices with metal silicide using pre-amorphization implants

A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.

Semiconductor devices

A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer.

Methods of manufacturing semiconductor devices

Transistor structure of a semiconductor device

A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal.

Manufacturing method for semiconductor device

A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.

Methods for manufacturing semiconductor devices using etch stop dielectric layers and related devices

A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.

Non-volatile memory devices having resistance changeable elements and related systems and methods

A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.

Method for manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.

Method of manufacturing semiconductor device

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Seoul, South Korea

Sang-Bom Kang