Hyundai Electronics Industries Co. Ltd.

Hynix Semiconductor Inc.

Hynix Electronics Industries Co., Ltd.

Sang Bae Yi

Jae Seung Choi

Sung Youn Kim

Jung Hoon Seo

The present invention relates to an array of flash memory cells whose unit cell includes a single transistor of MONOS/SONOS structure (Metal/poly-Silicon Oxide Nitride Oxide Semiconductor) and to data programming and erasing using the same. The array of the flash memory cells includes a plurality of flash memory cells arranged in a form of a matrix. The matrix includes a plurality of word lines arranged in one line direction and connected to gates of the flash memory cells is a row, a plurality of selection lines arranged in a direction perpendicular to the word lines and connected to the sources of the flash memory cells arranged in a column, and a plurality of bit lines arranged in a direction parallel to the selection lines and connected to the drains of the flash memory cells of the same column. To program and erase the cells, different biasing conditions are applied to the word lines, selection lines, bit lines, and the wells of the transistors.

Array of flash memory cells and data program and erase methods of the same

Disclosed is a nonvolatile memory device comprising a semiconductor substrate defining first and second active regions arranged in one direction; a first gate insulating layer and a floating gate deposited on the first and second active regions in a predetermined pattern; a second gate insulating layer and a control gate line deposited in one direction perpendicular to the first and second active regions and covering the floating gate; first impurity regions formed in the first and second active regions at one side of the control gate line; second impurity regions formed in the first and second active regions at other side of the control gate line; first contact plugs contacted with the first impurity regions; and a common conductive line formed in one direction on the semiconductor substrate at the other side of the control gate line, for connecting the second impurity regions of the first and second active regions.

Nonvolatile memory device and method for fabricating the same

A flash memory cell array and a method for programming and erasing data using the same are provided, in which problems related to over-erasing and disturbance are overcome and a cell area per bit is small to obtain high reliability and high packing density. In a flash memory cell array which includes a plurality of flash memory cells arranged in a matrix form, each of the cells including a selection transistor and a memory transistor serially connected with each other, a method for programming data using the flash memory cell array comprising the steps of setting a threshold voltage of the selection transistors at an initial threshold voltage level V before programming the flash memory cells at N bit data level (level of 2 ), selecting a cell for programming from the flash memory cells, and setting a threshold voltage level corresponding to the N bit in the selection transistors so that the memory transistor of the selected flash memory cell is programmed at a particular level among the N bit data level.

Flash memory cell array and method for programming and erasing data using the same

A method for fabricating a high voltage transistor includes the steps of: forming a plurality of drift regions on a semiconductor substrate of a first conductive type; implanting drift ions of a second conductive type into surfaces of the drift regions of the semiconductor substrate at a first depth; implanting drift ions of the second conductive type into the surfaces of the drift regions of the semiconductor substrate at a second depth deeper than the first depth; implanting first conductive channel stop ions into the semiconductor substrate thereby forming a space between the semiconductor substrate and the drift regions; forming a device isolation film on a surface of the semiconductor substrate into which the channel stop ions are implanted; forming a gate electrode by inserting a gate insulating film on the semiconductor substrate between the drift regions; and forming a source/drain impurity diffusion region of a second conductive type in the surface of the semiconductor substrate at both sides of the gate electrode.

Growing community of inventors

Chungcheongbuk-do, South Korea

Sang Bae Yi