Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Globalfoundries Inc.

Globalfoundaries Inc.

Sanford Chu

Purakh Raj Verma

Chit Hwei Ng

Lap Chan

Jia Zhen Zheng

Yisuo Li

Sung Mun Jung

Swee Tuck Woo

Eng Huat Toh

Yelehanka Ramachandramurthy Pradeep

Shao Kai

Jae Gon Lee

Guowei Zhang

Chung Foong Tan

Sia Choon Beng

Jianbo Yang

Kian Hong Lim

Shaoqiang Zhang

Ng Chit Hwei

Johnny Chew

Elgin Kiok Quek

Liang Choo Hsia

Pradeep Yelehanka

Jeoung Mo Koo

Kai Shao

Choon Beng Sia

Yeo Kiat Seng

Chunlin Zhu

Verma Purakh

Hwee Ngoh Chua

Jia Zhen

Shyue Seng Tan

Jagar Singh

Yung Fu Chong

Robert Fox

Ying Keung Leung

David Paul Brunco

Lee Wee Teo

Lup San Leong

Xu Yi

Chaw Sing Ho

Daniel Yen

Patrick Polakowski

Dina Triyoso

Johannes Mueller

Raymond Joy

Dina H Triyoso

Lili Cheng

Chen Liang

Liming Li

Yong Ju

Bin Yang

Han Xiao

Jeasung Park

Sajan Marokkey Raphael

Chew Kok Wai

Zheng Jia Zhen

Wensheg Qian

Chang Chuan Hu

Tan Li Jia

Tjoa Tjin Tjin

Bao Guang Wen

Chew Kok-Wai

Chit Hwei

Wu-Guan Ping

Cheng-Wei Hua

Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area.

Integrated circuits with resistor structures formed from MIM capacitor material and methods for fabricating same

Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Integrated circuits including a MIMCAP device and methods of forming the same for long and controllable reliability lifetime

An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Semiconductor structure including capacitors having different capacitor dielectrics and method for the formation thereof

A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer.

P-channel flash with enhanced band-to-band tunneling hot electron injection

Methods for forming FIN-shaped field effect transistors (FINFETs) capable of withstanding high voltage applications and the resulting devices are disclosed. Embodiments include forming a source and a drain on a substrate, forming a thin body (FIN) on the substrate and connecting the source and the drain, forming a gate over top and side surfaces of a first part of the FIN, thereby defining a drain-side FIN region of the FIN between the gate and the drain, and forming a shielding region over top and side surfaces of a second part of the FIN in the drain-side FIN region.

High voltage FINFET structure

A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls.

Channel surface technique for fabrication of FinFET devices

A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness T. A capping layer is formed on the substrate having a formed thickness T. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness T. The thickness of the capping layer is adjusted from Tto about a target thickness T.

Dielectric stack

A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.

EEPROM cell

A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.

Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region.

Asymmetrical transistor device and method of fabrication

A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.

Semiconductor structure including high voltage device

Growing community of inventors

Singapore, Singapore

Sanford Chu