Infinera Corporation

Nortel Networks Corporation

Sandy Thomson

Han Henry Sun

Yuejian Wu

Kuang-Tsan Wu

John Duncan McNicol

Mehdi Torbatian

Mehdi Karimi

Paul MacDonald

Scott G Pringle

Deyuan Chan

Ting-Kuang Chiang

David J Krause

Ahmed Awadalla

Patrice Brissette

Stanley H Blakey

Scott Pringle

Ruibin Jin

Alexander Kaganov

Eric Hall

Sofia Amado

Aroutchelvame Mayilavelane

Christopher Fludger

Consistent with the present disclosure, multiple forward error correction (FEC) encoders are provided for encoding a respective one of a plurality of data streams. A mechanism is provided to mix or interleave portions of the encoded data such that each subcarrier carries information associated with each data stream, as opposed to each subcarrier carrying information associated with only a corresponding one of the data streams. As a result, both higher SNR and low SNR optical subcarriers carry such information, such that errors occurring during transmission are distributed and not concentrated or limited to information associated with a single data stream. Accordingly, at the receive end, each FEC decoder decodes information having a similar overall error rate. By balancing the error rates across each FEC encoder/decoder pair, the overall ability to correct errors improves compared to a system in which mixing or interleaving is not carried out.

Methods and apparatus for sub-carrier interleaving to improve overall forward error correction

Consistent with the present disclosure, an encoder circuit is provided at a transmit side of an optical fiber link that maps an input sequence of bits of fixed length k a sequence of symbols of a codeword of length n, such that the symbols of the codeword define a predetermined transmission probability distribution. Preferably, each symbol of the codeword is generated during a corresponding clock cycle, such that after n clock cycles, a complete codeword corresponding to the input bit sequence is output. On a receive end of the link, a decoder is provided that outputs the k-bit sequence every n clock cycles. Accordingly, buffers need not be provided at the output of the encoder and the input of the decoder, such that processing of the input sequence, codewords, and output sequence may be achieved efficiently without large buffers and complicated circuitry. Moreover, the input sequence, with any binary alphabet may be matched to a desired output distribution with any arbitrary alphabet. Accordingly, probabilistic constellation shaping may be achieved over constellations of arbitrary size. In addition, relatively long codewords, may be encoded and decoded with the apparatus and method disclosed herein. Accordingly, for a fixed SNR a higher SE (more bits per symbol) can be achieved. Alternatively, for a fixed SE, a lower SNR may be sufficient. Moreover, the resulting SE may be finely tailored to a particular optical link SNR to provide data transmission rates that are higher than the low order modulation formats that would otherwise be employed for optical signals carried by such links.

Distribution matching for probabilistic constellation shaping with an arbitrary input/output alphabet

A low-density parity-check (LDPC) decoder may comprise a shift register configured to receive LDPC coded data, perform an iteration associated with decoding the LDPC coded data, and provide a result of performing the iteration. The shift register may include a quantity of lanes corresponding to a quantity of data words received by the shift register at a particular clock cycle, a quantity of stages corresponding to a quantity of clock cycles needed to perform the iteration, a quantity of storage elements, associated with storing the data words during the iteration, and a set of check node elements associated with updating the data words during the iteration. The quantity of stages times the quantity of lanes may be greater than the quantity of storage elements by a particular number of storage elements. The particular number of storage elements may be displaced by the set of check node elements.

Efficient storage architecture for low-density parity-check decoding

A low-density parity-check (LDPC) decoder may receive LDPC coded data. The LDPC decoder may perform a decoding iteration associated with decoding the LDPC coded data. The decoding iteration may be performed by processing a group of layers. Each layer may include a corresponding set of check node elements, and may be processed by causing each check node element, of the set of check node elements corresponding to the layer, to update a set of variable node elements, connected to the check node element and associated with the LDPC coded data, based on a check node function associated with the check node element. The decoding iteration may be performed such that each layer is processed in parallel, and such that each check node element updates the corresponding set of variable node elements in parallel. The LDPC decoder may provide a result of performing the decoding iteration.

Code design and high-throughput decoder architecture for layered decoding of a low-density parity-check code

An optical receiver may receive a data stream, and may decode the data stream using a first iterative forward error correction (FEC) decoder. The optical receiver may determine whether to further decode the data stream using the first iterative FEC decoder or a second iterative FEC decoder that is different from the first iterative FEC decoder. The optical receiver may selectively perform a first action or a section action based on determining whether to further decode the data stream. The first action may include providing the data stream to the first iterative FEC decoder or the second iterative FEC decoder for further decoding when the data stream is to be further decoded. The second action may include preventing the data stream from being provided to the first iterative FEC decoder or the second iterative FEC decoder when the data stream is not to be further decoded.

Partitioning forward error correction decoding iterations to accommodate multiple data streams

An optical receiver may receive input signals carried by sub-carriers, and may apply test phases to each input signal. The optical receiver may determine error values, associated with test phases, for each input signal. The optical receiver may calculate updated metric values, associated with the test phases, for a particular input signal, based on a first error value and a second error value. The first error value may be associated with a first sub-carrier, and the second error value may be associated with a second sub-carrier. The optical receiver may compare the updated metric values associated with the particular input signal, and may determine a test phase that represents an estimated phase, associated with the particular input signal, based on the comparison. The optical receiver may determine a phase estimate value based on the test phase, and may provide the phase estimate value to modify the particular input signal.

Estimating phase using test phases and interpolation for modulation formats using multiple sub-carriers

An optical receiver may receive input signals carried by respective sub-carriers. The optical receiver may determine, based on the input signals, a compensation value to be used to modify an input signal. The optical receiver may use the compensation value to adjust the input signal to form a modified input signal. The compensation value may be used to modify a frequency or a phase of the input signal. The optical receiver may determine, based on the modified input signal, a phase estimate value that represents an estimated phase associated with the input signal. The optical receiver may combine the compensation value and the phase estimate value to form a phase adjustment signal, may combine the input signal and the phase adjustment signal to form an output signal, and may output the output signal.

Frequency and phase compensation for modulation formats using multiple sub-carriers

In one implementation, a device may include a voltage regulator circuit, a data processing circuit, and an error correction circuit, where the error correction circuit may correct errors in data processed by the data processing circuit to obtain error-corrected data and output an error-corrected version of the processed data. Additionally, an error monitor circuit may output an error signal indicative of a level of the errors in the processed data. A control circuit may receive the error signal and control the voltage regulator circuit to adjust, based on the error signal, the supply voltage to the data processing circuit. In some implementations, the control circuit may also base its decision to control the voltage regulator circuit based on available timing margins in the data processing circuit.

Adaptive voltage scaling based on the results of forward error correction processing

A system is to receive a word on which to perform error correction; obtain segments, from the word, each segment including a respective subset of samples; update, on a per segment basis, the word based on extrinsic information associated with a previous word; identify sets of least reliable positions (LRPs) associated with the segments; create a subset of LRPs based on a subset of samples within the sets of LRPs; generate candidate words based on the subset of LRPs; identify errors within the word or the candidate words; update, using the extrinsic information, a segment of the word that includes an error; determine distances between the candidate words and the updated word that includes the updated segment; identify best words associated with shortest distances; and perform error correction, on a next word, using other extrinsic information that is based on the best words.

Iterative forward error correction (FEC) on segmented words using a soft-metric arithmetic scheme

A system is configured to receive a block of symbols, associated with a phase-modulated signal that includes data symbols that correspond to a payload associated with the signal, and control symbols; process the control symbols to identify an amount of phase noise associated with the control symbols; reset a phase, associated with each of the data symbols, based on the amount of phase noise and a reference phase; interleave the respective data samples, of each of the data symbols with other data samples, where the interleaved respective data samples cause errors, associated with the respective data samples, to be spread out among the other data samples and reduces an error rate relative to a prior data rate that existed before the interleaving; and perform forward error correction on the interleaved respective data samples.

Coherent detection using coherent decoding and interleaving

A system, method, and apparatus is disclosed for interpolation of an output of an analog to digital converter (ADC) to enable operation of the ADC at a sampling rate that is independent of the sampling rate for a DSP core so as to efficiently enable operation at higher date rates. According to one of the embodiments, an interpolation circuit is coupled between the ADC and DSP core and receives a first plurality of samples of data at the first data rate from the ADC and supplies a plurality of samples of second data at a second data rate to the DSP core; the second data rate being less than the first data rate. According to one of the embodiments, the interpolation circuit includes a memory and a FIR filter circuit having filter tap coefficient values selected to provide attenuation at high frequencies to reduce aliasing noise.

Method, system, and apparatus for interpolating an output of an analog-to-digital converter

In one aspect a system and method for providing a multi-port memory having a plurality of read ports, each read port including a filter coefficient value representing a dispersion compensation value associated with an optical link. The method includes processing an input optical signal using the filter coefficient values in the multi-port memory to generate an output optical signal for transmission on the optical link.

Dispersion compensation in optical systems

A data regenerator for regenerating a data signal, including a convertor for converting a received data signal into a binary data signal in dependence on conversion parameters, an error corrector for correcting errors in the binary data signal based on error correction code contained in the binary data signal to produce a corrected binary data signal, and a performance monitor for comparing the corrected binary data signal with an uncorrected representation of the binary data signal to determine information about the relative number of logic'1's and logic '0's that have been corrected by the error corrector and output a feedback signal representative of the relative number, wherein the convertor adjusts at least some of the conversion parameters in dependance on the feedback signal.

Receiver monitoring and optimization using forward error correction information

A clock divider circuit for generating an output clock signal derived from an input clock signal with the output clock signal having a selected frequency and duty cycle. The clock divider circuit comprises a linear shift register with a feedback loop. Data is shifted through the stages of the linear shift register in response to the input clock signal being applied at a clock input port. The output clock signal is derived from the data outputs on selected stages in the linear shift register. In one aspect, the clock divider circuit divides a 667 MHz input clock signal to generate a 44 MHz output clock signal having a 50% duty cycle. In another aspect, the clock divider circuit divides a 669 MHz input clock signal to generate a 45 MHz output clock signal.

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Ottawa, Canada

Sandy Thomson