Stmicroelectronics (grenoble 2) Sas

Stmicroelectronics (alps) Sas

Sandrine Nicolas

Danika Perrin

Serge Ramet

Michel Ayraud

Thierry Masson

Colette Morche

Jean-Baptiste Casanova

Reiner Welk

Damien Giot

Cedric Rechatin

The present description concerns a method of controlling an analog-to-digital converter, wherein most significant bits are determined by successive approximations implementing a first digital-to-analog converter and a second digital-to-analog converter. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of the first converter with a third digital-to-analog converter and by applying a second ramp to the output of the second converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first and second converters at the end of the successive approximations.

Method for controlling an analog-to-digital converter

In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.

Envelope detection

An electronic circuit comprises capacitive structures that are connected to one or a plurality of nodes, where each of the capacitive structures is formed by a capacitor or by a plurality of capacitors electrically connected in parallel. The electronic circuit further comprises additional capacitors that are each connected to the one or plurality of nodes. For at least one distance between capacitors, the capacitive structures have a same average of values defined, for each capacitor of each capacitive structure, by the number of capacitors of the circuit connected to the one or plurality of nodes and located at the distance from the capacitor of the capacitive structure.

Electronic circuit with a set of weighted capacitances

An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.

Biasing current regularization loop stabilization

An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.

Method and device for self-biased and self-regulated common-mode amplification

A receiver circuit for a differential input signal, may include a divider bridge having first and second ends, a midpoint therebetween, and intermediate points on either side of the midpoint. The divider bridge is coupled to receive the differential input signal at the first and second ends. A current generator is coupled to the divider bridge and configured to generate compensation currents associated respectively with components of the differential input signal. The divider bridge is configured to receive the compensation currents respectively at the intermediate points, and generate a compensated differential signal between the intermediate points.

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Saint Egreve, France

Sandrine Nicolas