Intermolecular, Inc.

Elpida Memory, Inc.

International Business Machines Corporation

Tokyo Electron Limited

Hypernex, Inc.

Other

Elpidia Memory, Inc.

Sandra Guy Malhotra

Hanhong Chen

Hiroyuki Ode

Tony P Chiang

Pragati Kumar

Wim Deweerd

Imran Hashim

Edward L Haywood

Sunil Shanker

Xiangxin Rui

Thomas R Boussie

Sean Barstow

Prashant B Phatak

David E Lazovsky

Fenton Read McFeely

Andrew Herbert Simon

Stephen Mark Rossnagel

Mitsuhiro Horikawa

Kurt H Weiner

Kenichi Koyanagi

Wen Wu

Nobi Fuchigami

Cyril Cabral, Jr

Timothy Joseph Dalton

Hariklia Deligianni

Indranil De

Chi-I Lang

Yumiko Kawano

Mahadevaiyer Krishnan

Chao-Kun Hu

Jinhong Tong

Xiaoyan Shao

Anh Duong

Gert J Leusink

Kenneth Parker Rodbell

Nitin Kumar

Anna Wanda Topol

Carlos Juan Sambucetti

Tatsuo Hatano

Gerrit J Leusink

Kenji Suzuki

Hideaki Yamasaki

Atsushi Gomi

John Gerard Gaudiello

Randolph F Knarr

Zachary M Fresco

John Jacob Yurkas

Gaurav Verma

Tsukasa Matsuda

Philippe M Vereecken

Monica Sawkar Mathur

Emmanuel P Guidotti

Daniel C Edelstein

Yun Yu Wang

Katherine Lynn Saenger

Eugene John O'Sullivan

David Lee Rath

Chandrasekhar Narayan

Toshiyuki Hirota

Shyng-Tsong Chen

Kaushik Arun Kumar

Panayotis Constantinou Andricacos

Michael F Lofaro

Michael Wayne Lane

Maurice McGlashan-Powell

Wei-Tsu Tseng

Judith Marie Rubino

Masahito Sugiura

Ronald Dean Goldblatt

Fen Fen Jamin

Kenneth M Davis

Steffen K Kaldor

David S Kurtz

Ryan C Clarke

Yoram Schwarz

Oscar Van Der Straten

Richard Stephan Wise

Thomas M Shaw

Conal Eugene Murray

Vincent James McGahay

Zhi-Wen Sun

Michael D Armacost

Roy Arthur Carruthers

William Francis Landers

Masamichi Hara

Robert Rosenberg

Eric Gerhard Liniger

Lynne Marie Gignac

Cory Wajda

Charles Robert Davis

Mitsuhiro Tachibana

Brett H Engel

John Bruley

Wilma Jean Horkans

Peter Stevens Locke

Scott W Crowder

Tina Jane Wagner

Stefanie Ruth Chiras

Keith Thomas Kwietniak

Milan Paunovic

A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region

A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

DRAM MIM capacitor using non-noble electrodes

Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

High work function, manufacturable top electrode

A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.

Adsorption site blocking method for co-doping ALD films

A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include 'bulky' ligands.

Methods for reproducible flash layer deposition

Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Nonvolatile memory elements

Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

Resistive-switching nonvolatile memory elements

This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Enhanced work function layer supporting growth of rutile phase titanium oxide

This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Yttrium and titanium high-K dielectric film

Yttrium and titanium high-k dielectric films

Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate relative to at least one other region of the substrate. Processing systems are described that include numerous processing modules. The modules include a site-isolated reactor (SIR) configured for one or more of molecular self-assembly and combinatorial processing of a substrate.

Processing substrates using site-isolated processing

Growing community of inventors

Fort Collins, CO, United States of America

Sandra Guy Malhotra