National Semiconductor Corporation

Sandra G Schneider

D Kevin Covey

Roy K Yamanouchi

Donald K Covey

A hierarchial hardware flowchart methodology for design of integrated circuits utilizes repetitious symbols in a first level flowchart with a single macro flowchart symbol per instance that conveys the same information, resulting in a two-dimensional flowchart. This allows the same information to be conveyed in a smaller, more readable format.

Hierarchical hardware flowchart using symbolic macros

The present invention provides a structured integrated circuit design methodology. The methodology is based on describing a two-phase logic function using a high level behavioral description flow chart, properly sizing devices to be used in the circuit for speed and reducing trial and error in circuit layout implementation using novel chip planning techniques. The methodology begins with the definition of signal types based on the circuit function that creates a particular signal and the type of input signal that feeds the circuit function. A rigid set of rules is then established for use of the signal types. Next the technical specification of the two-phase logic function is defined and utilized to create a behavioral flow chart using defined symbols. An associated database of corresponding Boolean equations is then created that defines the parameters of the various elements of the flow chart. The Boolean equations are then converted to a logic diagram either by coded state assignment or by direct implementation. The resulting logic diagram is then analyzed for speed utilizing a Figures of Merit technique for establishing device sizes. The resulting circuit design may then be carried through to layout utilizing conventional computer aided design (CAD) tools.

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San Jose, CA, United States of America

Sandra G Schneider