Xilinx, Inc.

Sandor S Kalman

Vinay Verma

Jason Helge Anderson

Taneem Ahmed

Raymond Kong

Sanjeev Kwatra

Sudip K Nag

Gitu Jain

Christopher H Kingsley

Satyaki Das

Jason H Anderson

Kamal Chaudhary

Anirban Rahut

Sankaranarayanan Srinivasan

W Story Leavesley, Iii

Richard Yachyang Sun

Rajeev Jayaraman

Madabhushi V R Chari

Douglas P Wieland

Hasan Arslan

George L McHugh

Jitu Jain

Hui Xu

Gi-Joon Nam

Jennifer Zhuang

A method, apparatus, and computer readable medium for synchronizing a main thread and a slave thread executing on a processor system are disclosed. For example, the method includes the following elements: transitioning the slave thread from a sleep state to a spin-lock state in response to a wake-up message from the main thread; transitioning the slave thread out of the spin-lock state to process a first work unit from the main thread; determining, at the main thread, an elapsed time period until receipt of a second work unit for the slave thread; transitioning the slave thread to the spin-lock state if the elapsed time period satisfies a threshold time period; and transitioning the slave thread to the sleep state if the elapsed time period does not satisfy the threshold time period.

Thread synchronization by transitioning threads to spin lock and sleep state

Within a system comprising a plurality of processors and a memory, a method of determining routing information for a circuit design for implementation within a programmable integrated circuit can include determining that nets of the circuit design comprise overlap and unrouting nets comprising overlap. A congestion picture can be determined that comprises costs of routing resources for the integrated circuit wherein the cost of a routing resource comprises a measure of historical congestion and a measure of current congestion, and wherein unrouted nets do not contribute to the measures of current congestion in the congestion picture. The method further can include concurrently routing a plurality of the unrouted nets via the plurality of processors executing in parallel according to the congestion picture and storing routing information for nets of the circuit design in the memory.

Multi-threaded deterministic router

A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.

In one embodiment, a method for routing of a circuit design netlist is provided. A processing cost is determined for each net in the netlist. A plurality of regions are defined for the target device such that the total processing costs of nets are balanced between the plurality of regions. Concurrent with routing one or more nets of a first one of the plurality of regions, one or more nets are routed in at least one other of the plurality of regions. Synchronization and subsequent routing are performed for unrouted nets of the netlist.

Parallel process optimized signal routing

A method is provided for routing a circuit design netlist. Nets of the netlist are grouped into a plurality of sub-netlists. For each sub-netlist, nets of the sub-netlist are routed as a function of congestion between nets of the sub-netlist. Congestion between nets of other sub-netlists in the plurality of sub-netlists is not taken into account. If two or more nets of the netlist are routed through the same routing resource, a global congestion history data set is updated to describe congestion between all nets in the netlist, and the two or more nets of the netlist are unrouted. The two or more nets are each rerouted as a function of the global congestion history data set and congestion between nets of the same sub-netlist as the net.

Parallel signal routing

In one embodiment of the invention, a processor-implemented method is provided for routing of a partially routed circuit design. Modified signals of the partially routed circuit design are determined. A first set of routing constraints are applied by the processor to the unmodified signals of the circuit design. For each logic block of the circuit design, the number of the modified signals and the number of the unmodified signals connected to the logic block are determined. In response to one of the logic blocks having a ratio of the number of modified signals to the number of unmodified signals greater than a threshold ratio, the routing constraints are removed by the processor from one or more of the unmodified signals of the one of the logic blocks. The partially routed circuit design is then routed by the processor according to the remaining routing constraints, and the resulting netlist is stored.

Incremental placement and routing

Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable interconnects. A path is determined from the source to the destination for each net of the logic design. The path is through a sequence of the programmable interconnects having types that correspond to each type in the ordered set of a selected pattern. A description is output of the path for each of the nets.

Patterns for routing nets in a programmable logic device

A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty sites of the target device within which the circuit design is to be implemented can be identified. The method also can include determining whether each of the plurality of empty sites of the target device has a routing conflict according to the routing information of the circuit design and generating a list specifying each empty site of the target device that has a routing conflict.

Method of placement for iterative implementation flows

Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device is described. In one example, a definition of the pre-implemented circuit design is obtained (). The definition includes a first physical implementation and a first logical implementation. A second logical implementation is produced () for an instance of the pre-implemented circuit design using the first logical implementation. A second physical implementation is produced () for then instance of the pre-implemented circuit design using the first physical implementation.

Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device

A method for completing the routing of a partially routed design is provided. The unrouted pins are routed to generate a first plurality of nets that may contain shorts or overlaps between the nets. The nets are analyzed to obtain timing information, and then divided into a set of critical and a set of non-critical nets. The non-critical nets are hidden, and the critical nets are rerouted to remove overlaps. The non-critical nets are then unhidden. The non-critical nets and rerouted critical nets are then rerouted so as to remove overlaps.

Incremental routing in integrated circuit design

A method for post-layout timing optimization is disclosed. The method performs timing analysis on a design to obtain timing information such as critical paths and slack values. Incremental placement based on the timing information is performed. A new routed design is generated by applying incremental routing to the result of incremental placement. The routed design is stored if its performance is better than the previous routed design. The above steps are repeated until a predetermined criterion is met.

Post-layout optimization in integrated circuit design

A method and apparatus for determining routing feasibility of a plurality of nets. Each net has an associated set of one or more routing solutions, wherein each solution specifies one or more routing resources consumed by the net. A liveness Boolean function is generated having variables that represent respective net/solution pairs. If there exists a set of values for the variables such that at least one of the variables for each net is logically true, then the liveness function is true. An exclusivity function is generated using the variables that represent the net/solution pairs. If there exists at least one set of values for the variables such that no resource is used is by more than a predetermined number of nets, then the exclusivity function is true. The nets are routable using the provided solutions if there is one set of values for the variables such that both the liveness and exclusivity functions are true.

Method and apparatus for testing routability

The present invention provides a new method to handle power and ground signals in modular design of programmable logic devices. During module implementation, the power and ground signals of each module are associated with area constraint properties. When performing routing in the module implementation phase, the power and ground signals together with regular local signals of the module are routed in accordance with their respective area constraint properties. However, the area constraint properties of the power and ground signals are removed during assembly phase while the area constraint properties of the local signals are retained.

Signal routing in programmable logic devices

Routing algorithms can be modified to increase the number of programmable interconnect points (PIPs) used in a routing pattern. A file is set up to store information on whether a PIP has been covered. The cost of a node can be decreased by a predetermined value if two nodes are connected by an uncovered PIP. In another embodiment, a file is set up to store a count for each PIP. The count is increased each time the PIP is used in a routing. The cost of a node can be increased by multiplying a predetermined value and the count of a PIP associated with the node.

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Santa Clara, CA, United States of America

Sandor S Kalman