Cadence Design Systems, Inc.

Sandipan Ghosh

Karun Sharma

Chayan Majumder

Hui Xu

Pawan Fangaria

Rajan Arora

Anil Kumar Arya

Yu Liu

Hongzhou Liu

Henry K Yu

Yinnie Lee

Hitesh Marwah

Joshua Alexander Baudhuin

Gary Matsunami

Anjna Khanna

Juno Lin

Ron Pyke

Allen You

Chris (Shyh-Chang) Lin

Rahaprian Premavathi Mudiarasan

Jiulong Zhang

Thomas Richards

Arbind Kumar

Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic design library including a plurality of design rules. Embodiments may include generating a routing graph, based upon, at least in part, the plurality of design rules, wherein the routing graph is a virtual representation of all of the available routing space for all routing layers associated with an electronic design. Embodiments may further include dynamically updating the routing graph at a graphical user interface, based upon, at least in part, a creation of a routing segment or a via at the graphical user interface.

System and method for routing in an electronic design

Disclosed is an approach for implementing placement for an electronic design, where when a dragged object is moved into a desired area, existing objects in that location are automatically moved as necessary in correspondence to the movement of the dragged object. Existing objects are only moved if they are causing a spacing violation or overlap with the dragged object being moved, either directly or indirectly.

Method, system, and computer program product for rearrangement of objects within an electronic design

Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems, and using information about instances that have been included in the design. In particular, the present embodiments allow for the automatic creation of WSPs by examining heights and placement orientations of instances, along with the width, spacing, and colors of instance pins and blockages. In these and other embodiments, techniques are provided for filling gaps between generated tracks, as well as for generating tracks to account for the possibility of flipped or mirrored instances.

Generating width spacing patterns for multiple patterning processes using instances

A system and method are provided for selective application and expeditious reconciliation of constraints within a hierarchy of circuit design constraints. A semi-transparent constraint editor user interface is provided in contextual registration near detected violations during editing interactions with a circuit design. The constraint editor provides a simplified representation of a lookup order of a hierarchy of constraints applicable to an object related to the detected violation. The user is then able to easily modify constrained values within the lookup order, modify the lookup order, or modify the editing interaction to reconcile the violation expeditiously all while maintaining context within the circuit design.

System and method for selective application and reconciliation of hierarchical ordered sets of circuit design constraints within a circuit design editor

Methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits. Embodiments provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams, and modify and arrange circuit items with respect to one another in congested layouts and schematic diagrams. Additional embodiments are directed to enabling EDA commands and the like to have context sensitivity, neighborhood awareness, and/or an ability to anticipate intentions of the user.

Methods, systems, and computer-program products for item selection and positioning suitable for high-altitude and context sensitive editing of electrical circuits

According to various embodiments of the invention, a system and method for editing process rules for circuit design through a graphical editor is provided. In some embodiments, the graphical editor is a circuit design tool that provides the user of the tool, such as a circuit designer or process engineer, the ability to visualize, modify, create, or remove process rules through a graphical user interface ('GUI'). These process rules, also known as constraints or circuit design constraints, relate to the layout of circuits and is grouped into constraint groups (also known as 'circuit design constraint groups') that can be associated to specific circuit design objects.

System and method for process rules editors

Embodiments of the invention provide system and methods for EDA tools. Specifically, some embodiments of the invention provide an input infrastructure for EDA tools that gathers pertinent information surrounding an input cursor's present locality (or neighborhood) and then analyzes the pertinent information in view of an issued command to automatically determine suitable targets or subsequent operations that a user of the EDA tool may want to select next.

System and method for aperture based layout data analysis to achieve neighborhood awareness

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New Delhi, India

Sandipan Ghosh