International Business Machines Corporation

Cornell University

Other

Samsung Electronics Co., Ltd.

Sandip Tiwari

Steven Lorenz Wright

Devendra K Sadana

Kevin K Chan

Arvind Kumar

Ghavam G Shahidi

Christopher Peter D'Emic

Jeffrey John Welser

Bijan Davari

Michael A Tischler

Steven J Holmes

Paul Michael Solomon

Jerry M Woodall

Howard L Kalter

Jeremy H Burroughes

Jian J Xu

Erin C Jones

Donald Stimson Bethune

Thomas N Jackson

Bojan Robert Ilic

Mark S Milshtein

Brian A Bryce

Mark C Reuter

Samuel Jonas Wind

John Batey

William H Price

Masanori Murakami

Theoren Perlee Smith, Iii

Ravishankar Sundararaman

Keith E Fogel

Charles Thomas Black

Daniel Michael Kuchta

Christopher Kemper Ober

Evan L Schwartz

Allan Mark Hartstein

James Anthony Misewich

Dennis L Rogers

Hans S Rupprecht

Joachim Norbert Burghartz

Choong-Man Lee

Jin-kyun Lee

John D Crow

Gregory T Baxter

Moon-Kyung Kim

Kwang Su Choe

Soo-Doo Chae

Paul Michael Kozlowski

Margaret Paggi Manny

Robert E Bendernagel

Steve Koester

Raymond M Sicina

Roger Morton Macfarlane

Sang Hyeon Lee

Chung Woo Kim

Reuben T Collins

Moonkyung Kim

Joshua Mark Rubin

Wei Min Chan

Sanjay Sethi

A method for forming patterns of organic polymer materials. The method can be used to form a layer with two patterned organic polymer materials. The photoresist and solvents used in the photoresist deposition and removal steps do not substantially affect the organic polymer materials.

Methods of making patterned structures of materials, patterned structures of materials, and methods of using same

In one embodiment there is set forth a method comprising providing a semiconductor structure having an electrode, wherein the providing includes providing a phase transition material region and wherein the method further includes imparting energy to the phase transition material region to induce a phase transition of the phase transition material region. By inducing a phase transition of the phase transition material region, a state of the semiconductor structure can be changed. There is further set forth an apparatus comprising a structure including an electrode and a phase transition material region, wherein the apparatus is operative for imparting energy to the phase transition material region to induce a phase transition of the phase transition material region without the phase transition of the phase transition material region being dependent on electron transport through the phase transition material region.

Phase transition memories and transistors

A probe for scanned probe microscopy is provided. The probe includes a cantilever beam and a tip. The cantilever beam extends along a generally horizontal axis. The cantilever beam has a crystal facet surface that is oriented at a tilt angle with respect to the generally horizontal axis. The tip projects outwardly from the crystal facet surface.

Scanned probe microscopy (SPM) probe having angled tip

Mechanical devices having bistable positions are utilized to form switches and memory devices. The devices are actuatable to different positions and may be coupled to a transistor device in various configurations to provide memory devices. Actuation mechanisms include electrostatic methods and heat. In one form, the mechanical device forms a gate for a field effect transistor. In a further form, the device may be a switch that may be coupled to the transistor in various manners to affect its electrical characteristics when on and off. The memory switch in one embodiment comprises side walls formed with tensile or compressive films. A cross point switch is formed from a plurality of intersecting conductive rows and columns of conductors. Actuatable switches are positioned between each intersection of the rows and columns such that each intersection is independently addressable.

Shape memory device

A method of creating a probe for scanned probe microscopy is disclosed. The method includes providing a wafer having a support wafer layer and a device layer. The method includes masking the wafer with a masking layer. The method includes removing a portion of the masking layer at the device layer. The method includes etching the wafer along the portion of the masking layer that has been removed to create a crystal facet surface that is oriented at a tilt angle. The method includes epitaxially growing a tip along the crystal facet surface.

An electro-mechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.

Electro-mechanical transistor

A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.

Compact SRAMs and other multiple transistor structures

According to an aspect of the invention, a device structure is provided where charging and discharging occur in a trapping region formed by a stack of films that is placed on the back of a thin silicon channel. Uncoupling the charging mechanisms that lead to the memory function from the front gate transistor operation allows efficient scaling of the front gate. But significantly more important is a unique character of these devices: these structures can be operated both as a transistor and as a memory. The thin active silicon channel and the thin front oxide provide the capability of scaling the structure to tens of nanometers, and the dual function of the device is obtained by using two voltage ranges that are clearly distinct. At small voltages the structure operates as a normal transistor, and at higher voltages the structure operates as a memory device.

Scalable nano-transistor and memory using back-side trapping

A gated metal oxide semiconductor field effect transistor (MOSFET) gain cell is formed with a flow channel for molecule flow. The flow channel is formed under the gate, and between a source and drain of the transistor. The molecule flow modulates a gain of the transistor. Current flowing between the source and drain is representative of charges on the molecules flowing through the flow channel. A plurality of individually addressable gain cells are coupled between chambers containing samples to measure charges on molecules in the samples passing through the gain cells.

Electronic gain cell based charge sensor

A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structure are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.

Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering

A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

Patterned SOI regions on semiconductor chips

The present invention is directed to a microelectric device and especially a Field effect transistor comprising a source, drain, channel, an insulating layer overlying said channel containing at least one closed cage molecule, said closed cage molecule being capable of exhibiting a Coulomb blockade effect upon application of a voltage between said source and drain. Two different microelectronic devices are described containing the closed cage molecule, a logic cell and a memory cell.

Molecular memory & logic

In a method for forming a three dimensional interconnected structure, sets of devices on receiver and donor semiconductor substrates. The donor substrate is implanted with two or more exfoliating implants, the substrates are bonded together to form a bonded structure that is heated until a portion of the donor substrate exfoliates from the bonded structure and leaves a residual portion of the donor bonded to the receiver. To form three dimensional interconnected integrated circuits from devices formed on donor and receiver substrates, the receiver devices are covered with a protective and bonding layer. Interconnect structures extending from the surface of the protective and bonding layer to the devices of the receiver are formed, and a donor is implanted with two or more exfoliating implants. After bonding and heating of the two substrates until a portion of the donor exfoliates from the bonded substrates, leaving a remaining layer of the donor bonded to the receiver, the resulting devices are interconnected in an integrated circuit.

Low temperature semiconductor layering and three-dimensional electronic circuits using the layering

A two transistor programmable logic cell is used in programmable logic devices. The cell has a backgate that holds charge to program one of the two transistors into a logic 1 or a logic 0 state. Programmable logic devices are scalable to fine geometries and high densities and may be programmed to perform multiple logic functions on the same substrate.

Dense backplane cell for configurable logic

Growing community of inventors

Ithaca, NY, United States of America

Sandip Tiwari