Intel Corporation

International Business Machines Corporation

Sandip Kundu

Sanjay Sengupta

Rajesh Galivanche

Vivek K De

James W Tschanz

Leendert M Huisman

Andreas Kuehlmann

Pascal Meinerzhagen

Srinivas Patil

Sitaram Yadavalli

Matthias Gruetzner

Arvind Srinivasan

Cordt W Starke

Dhiraj Goswami

Described are apparatuses and methods for detecting or repairing minimum-delay errors. The apparatus may include a minimum-delay error detector (MDED) to receive a clock signal and a data path signal and to detect a minimum-delay error (MDE) in the data path based on the received data path signal and the clock signal. The MDE may be repaired by adjusting one or more regional clock buffers coupled to the MDED. Further, the apparatus may include minimum-delay path replicas (MDPRs) used for detecting and repairing MDEs during normal system operations. Other embodiments may be described and/or claimed.

Apparatus and method for detecting or repairing minimum delay errors

According to some embodiments, provided are a pseudo-random sequence generator to generate a pseudo-random sequence of data values, a decoder to receive compressed weight values and to generate decompressed weight values, and a weighting unit to receive the pseudo-random sequence of data values, to receive the decompressed weight values and to weight the pseudo-random sequence of data values based on the decompressed weight values.

Weight compression/decompression system

A packaged component includes a pattern generator for generating successive random data patterns. The component further includes a programmable constraint correction module, coupled to the pattern generator, to replace undesirable random data patterns with desirable bit sequences to overcome bus contention problems in the generated random data patterns. The component further includes an integrated circuit device to be functionally tested. The device receives the constrained random data patterns from the constraint correction module and outputs a test result. The device further includes a programmable X-masking module coupled to the device receives and masks the test result by replacing unpredictable bit values in the received test result with predictable bit values. A signature analyzer coupled to the X-masking module receives the masked test result and compresses the test result into a signature. Then a comparator coupled to the signature analyzer compares the signature with a predetermined test result to determine whether the device is free of structural defects.

Dft technique for avoiding contention/conflict in logic built-in self-test

A generalized fault model. For one aspect, extracted faults may be modeled using a fault model in which at least one of the following is specified: multiple fault atoms, two or more impact conditions for a first set of excitation conditions, a relative priority of fault atoms within a set of fault atoms used to model the at least one extracted fault, a dynamic fault delay, and excitation conditions including at least a first mandatory excitation condition and at least a second optional excitation condition.

Generalized fault model for defects and circuit marginalities

A netlist model of a physical circuit is provided. The netlist model includes a virtual delay element, wherein the virtual delay element is coupled to an asynchronous circuit element.

Method and apparatus for modeling and circuits with asynchronous behavior

A double-edge-triggered flip-flop scan cell. The double-edge-triggered flip-flop scan cell provides the capability to capture and output data for each edge of a clock signal in a functional mode of a host integrated circuit. In a test mode, the double-edge triggered flip-flop scan cell enables test data to be scanned into and out of the scan cell to provide observability and controllability of the scan cell internal state.

Scan design for double-edge-triggered flip-flops

An approach for power supply noise modeling for test pattern development. For one aspect, conditions that may result in power supply noise-related failures are identified and the resulting faults are ranked.

Method and apparatus for power supply noise modeling and test pattern development

A computer processor includes a plurality of storage elements, such as logic gates and flip-flops, that are interconnected in a first configuration during normal operation of the processor. A plurality of selector elements connected to the storage elements are used to rearrange the storage elements into a second configuration upon entry into a low-power mode of operation. In general, the storage elements, when rearranged into the second configuration, form a chain through which data passes serially for storage in a storage device, such as a memory device or a hard drive.

System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation

A test system for structurally testing an integrated circuit device includes a pattern generator for generating successive random data patterns (scan chain). The test system further includes a constraint checker and corrector module, coupled to the pattern generator, to replace undesirable random data patterns (state elements joined together in the scan chain such that one state element is connected to a ground and the other state element is connected to a power supply) with desirable bit sequences to eliminate bus contention problems in the generated random data patterns. The test system further includes the integrated circuit device to be tested. The integrated circuit device receives the constrained random data patterns from the constraint checker and corrector module and outputs a test result. The test system further includes an X-masking module coupled to the integrated circuit device. The X-masking module receives the test result from the integrated circuit device, and it masks the test result by replacing unpredictable bit values (these are bit values generated due to not scanning some state elements in the scan chain) in the test result with predictable bit values. A signature analyzer coupled to the X-masking module receives the masked test result and compress the test result into a signature. Then a comparator coupled to the signature analyzer compares the signature with a predetermined test result to determine the functionality of the integrated circuit device.

Constrained signature-based test

A system and method is providing for sorting integrated circuits based upon their maximum operating frequency. More particularly, the incremental time required for a test signal to be flushed through a level sensitive scan design (LSSD) circuit is measured. The test method of the present invention measures scan flush delay in the integrated circuit in order to measure the frequency of the circuit. A free running reference clock and on-chip counter are used measure the flush delay time period. With this information a count/second parameter can be determined, indicating the speed at which the test bit is flushed through the scan chain. The lower the value of the parameter, the higher the operating frequency of the chip.

Technique for sorting high frequency integrated circuits

A system is provided with scanning capability that can capture data for each internal node at any predetermined machine cycle. The scanning mechanism scans a set of combinational logic and uses the system clock to gate the input to the scanning mechanism. A series of stages are provided in accordance with the number of internal nodes which are not externally connected, and provide input to an internal storage element. Each stage includes a scan latch for storing the data from the previous stages, as well as a latch to store data from the node associated with that particular stage. The cumulative data outputs from the previous stages are multiplexed with the data associated with the present stage and sequentially output, from a third latch, to subsequent stages. In this manner, the scan data is compiled for the internal nodes and output from the final stage in the sequential scanning system of the present invention. A test apparatus is connected to the scan inputs and outputs of the stages to record the scan data for subsequent analysis. The input latches in each stage are gated by the system clock and are capable of storing values for any given machine cycle.

System and method for testing internal nodes of an integrated circuit at

A technique for extracting a gate level logic model from transistor networks has been described. The resultant logic model can be technology dependent or technology independent, depending on control parameters and environment of the program. It handles all CMOS logic families including static, precharge, pass CMOS switching network and self-resetting families. The output gate level model can be used in variety of applications including but not limited to logic simulation, verification, test generation, debug, diagnosis, etc.

CMOS transistor network to gate level model extractor for simulation,

A test pattern generator includes a random pattern generator and a shift register. The random pattern generator generates a series of digits which are input to the shift register and stored therein. Each digit output by the random pattern generator has a probability of having a first value, such as representing '1'. The output probability of the random pattern generator is adjustable. The shift register has a plurality of outputs for outputting a test pattern comprising the stored digits. The shift register includes a series of latches and at least a first logic circuit connecting the output of the random pattern generator to the input of a first latch, or connecting the output of a latch to the input of a next adjacent latch. In a first state, the logic circuit has an output probability which is independent of the output probability of the random pattern generator. In a second state, the logic circuit has an output probability which is dependent on the output probability of the random pattern generator.

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Austin, TX, United States of America

Sandip Kundu