International Business Machines Corporation

Sandhya Koteshwara

Dong Chen

Krishnan Sugavanam

Manoj N Kumar

Hubertus Franke

Jose Eduardo Moreira

Pratap Chandra Pattnaik

Kattamuri Ekanadham

Paul Gregory Crumley

Jose G Castanos

A computer implemented method for assessing endpoint security includes identifying a size of exposed PCIe space corresponding to a system of interest comprising one or more endpoints, determining an observable state of correct functionality for the system, generating random transaction layer packets corresponding to the endpoint, injecting the generated transaction layer packets, monitoring the system following the injection of the generated transaction layer packets for erroneous patterns exhibited by the system, and reporting the erroneous patterns exhibited by the system. A corresponding computer program product and computer system are also disclosed.

Fuzzing based security assessment

Embodiments for managing a computing system are provided. A Root-of-Trust (RoT) device within the computing system is caused to boot. The computing system includes at least one peripheral device, and the RoT device is in operable communication with the at least one peripheral device and a management server. The at least one peripheral device is caused to at least partially boot. The RoT device is caused to retrieve a firmware image associated with the at least one peripheral device from the management server. The at least one peripheral device is caused to reboot utilizing the firmware image.

Methods and systems for creating root-of-trust for computing system components

A Reduced Instruction Set Computer ('RISC') supporting large-word operations in a computing environment is disclosed. In one implementation, in response to receiving one or more control signals from a central processing unit ('CPU'), a set of operations are executed on a state of a special purpose execution unit (&#x201c;SPU&#x201d;) having a plurality of SPU registers, the SPU being associated with the CPU and the state of the SPU having word widths of one or more of the plurality of registers being greater in size than word widths of a plurality of CPU registers of a computing system and a set of state-master bits to synchronize the state of the SPU and a state of the CPU. The results of the set of operations are stored in the plurality of CPU registers or an alternative set of the plurality of SPU registers.

Supporting large-word operations in a reduced instruction set computer ('RISC') processor

Described is a baseboard management controller (BMC). The BMC comprises a BMC flash storage storing firmware and an access permission table. The access permission table defines an access control policy for access requests to peripherals communicatively coupled to the BMC. The BMC further comprises an access control chip comprising one or more processors and a write-once memory. The write-once memory stores a copy of the access permission table. The access control chip is configured to manage access to the peripherals using the access permission table.

Growing community of inventors

White Plains, NY, United States of America

Sandhya Koteshwara