University of Rochester

Other

International Business Machines Corporation

Compaq Computer Corporation, Inc.

Sandhya Dwarkadas

Rajeev Balasubramonian

David H Albonesi

Michael L Scott

Arrvindh Shriraman

Alper Buyuktosunoglu

Evelyn Duesterwald

Grigorios Magklis

Gheorghe Calin Cascaval

Greg P Semeraro

Alper Buyuktosnoglu

Galen Clyde Hunt

Virendra J Marathe

Leonidas Kontothanassis

Michael F Spear

Hongzhou Zhao

Robert Stets

Nikos Hardavellas

A method and directory system that recognizes and represents the subset of sharing patterns present in an application is provided. As used herein, the term sharing pattern refers to a group of processors accessing a single memory location in an application. The sharing pattern is decoupled from each cache line and held in a separate directory table. The sharing pattern of a cache block is the bit vector representing the processors that share the block. Multiple cache lines that have the same sharing pattern point to a common entry in the directory table. In addition, when the table capacity is exceeded, patterns that are similar to each other are dynamically collated into a single entry.

Sharing pattern-based directory coherence for multicore scalability ('SPACE')

The present invention employs three decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary tables, which identify the threads with which conflicts have occurred; and a lazy versioning mechanism, which maintains the speculative updates in the local cache and employs a thread-private buffer (in virtual memory) only in the rare event of an overflow. The conflict summary tables allow lazy conflict management to occur locally, with no global arbitration (they also support eager management). All three mechanisms are kept software-accessible, to enable virtualization and to support transactions of arbitrary length.

Mechanism to support flexible decoupled transactional memory

In a transactional memory technique, hardware serves simply to optimize the performance of transactions that are controlled fundamentally by software. The hardware support reduces the overhead of common TM tasks&#x2014;conflict detection, validation, and data isolation&#x2014;for common-case bounded transactions. Software control preserves policy flexibility and supports transactions unbounded in space and in time. The hardware includes 1) an alert-on-update mechanism for fast software-controlled conflict detection; and 2) programmable data isolation, allowing potentially conflicting readers and writers to proceed concurrently under software control.

System and method for hardware acceleration of a software transactional memory

In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.

Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration

A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.

Dynamic reconfigurable memory hierarchy

Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.

Multiple clock domain microprocessor

Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals

Disclosed are a method and system for predicting future values of a target metric associated with a task executed on a computer system. The method comprises the steps of, over a given period of time, measuring at least one defined metric, transforming that measurement into a value for a predictor source metric, and using the value for the predictor source metric to obtain a predicted future value for said target metric. The preferred embodiment of this invention provides a flexible performance multi-predictor to solve the problem of providing accurate future behavior predictions for adaptive reconfiguration systems. The multi-predictor makes predictions about future workload characteristic by periodically reading available hardware counters. Also disclosed is a method and system for periodically reconfiguring an adaptive computer system by rescheduling tasks based on future behavior predictions.

Mechanism for on-line prediction of future performance measurements in a computer system

Disclosed are a method and system for predicting future values of a target metric associated with a task executed on a computer system. The method includes the steps of, over a given period of time, measuring at least one defined metric, transforming that measurement into a value for a predictor source metric, and using the value for the predictor source metric to obtain a predicted future value for said target metric. The preferred embodiment of this invention provides a flexible performance multi-predictor to solve the problem of providing accurate future behavior predictions for adaptive reconfiguration systems. The multi-predictor makes predictions about future workload characteristic by periodically reading available hardware counters. Also disclosed is a method and system for periodically reconfiguring an adaptive computer system by rescheduling tasks based on future behavior predictions.

The present invention discloses an apparatus and method for maintaining the coherence of data within a shared memory network including a plurality of nodes. The system utilizes processors monitoring the occurrence of particular processing events within a local memory storage area. Upon the detection of events indicating the change of status of a particular group of data, a comparison is made between a modified copy of the group of data and a clean copy of the group of data to detect any modifications made to the group of data. These modifications are entered into the clean copy of the group of data and processing continues.

Growing community of inventors

Rochester, NY, United States of America

Sandhya Dwarkadas