Infineon Technologies Ag

Sandeep Vangipuram

Frank Hellwig

Glenn Ashley Farrall

Darren Galpin

Albrecht Mayer

Ketan Dewan

Simon Cottam

Dietmar Koenig

Paul Hubbert

Trevor Bird

Shubhendu Mahajan

A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.

Systems, devices, and methods for dynamic allocation

An interconnect including an input couplable to a source, and an encoder coupled to the input. The encoder is configured to: group information that is received from the source via a same channel; size the grouped information to a common width; and apply protection to the sized grouped information.

Interconnection of protected information between components

A non-volatile memory (NVM) integrated circuit device includes a processing device and an NVM array of memory cells partitioned into a first physical region and a second physical region. The NVM integrated circuit device also includes a plurality of routing circuits, a first decoder associated with a first routing circuit, and a second decoder associated with a second routing circuit. The NVM integrated circuit device also includes a first programmable register coupled to the plurality of routing circuits, wherein the first programmable register is to store a first multi-bit value, the first multi-bit value programmed by the processing device to configure a first address range associated with the first decoder. The NVM integrated circuit device also includes a second programmable register coupled to the plurality of routing circuits, wherein the second programmable register is to store a second multi-bit value, the second multi-bit value programmed by the processing device to configure a second address range associated with the second decoder.

Flexible support for device emulation and bank swapping

A direct memory access (DMA) circuit is provided. The DMA circuit may include a plurality of groups of direct memory access channels, wherein each of the groups includes at least one DMA channel and a resource usage counter configured to count an execution time in which one of the DMA channels of the group is executed, and an arbiter configured to evaluate a value of the resource usage counter of a group upon a request for execution time by one of the DMA channels of the group, and, taking into account a result of the evaluation, to assign, delay assignment, or deny execution time for using the direct memory access to one of the groups.

Direct memory access circuit, microcontroller, and method of controlling a direct memory access

Some examples relate to a method. In the method, a write transaction is routed from a master device to a slave device through a communication path. The communication path includes a first bridge and a second bridge downstream of the first bridge. The first bridge and the second bridge are coupled to one another via an interface structure. The first bridge sets a write busy signal on the communication path when the write transaction is processed by the first bridge; and in response to the first bridge setting the write busy signal, the second bridge holds the write busy signal until the write transaction has been received by the slave device. Upon the slave device receiving the write transaction, the second bridge resets the write busy signal to propagate the reset write busy signal back to the master device through the first bridge.

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Bristol, United Kingdom

Sandeep Vangipuram