Qualcomm Incorporated

Sandeep Pande

Colin Beaton Verrilli

Natarajan Vaidhyanathan

Vinay Murthy

Geoffrey Carlton Berry

Matthew Simpson

Satish Singh

A machine learning (ML)-accelerator system-on-chip (SoC) is described. The ML-accelerator SoC includes a set of ML-accelerator cores. The ML-accelerator SoC also includes a network-on-chip (NoC) coupled to the set of ML-accelerator cores. The ML-accelerator SoC further includes an inference video post processing (infVPP) module coupled to the NoC. The ML-accelerator SoC also includes a video decoder coupled to the NoC.

Hardware-based image/video processing in machine learning-accelerator system-on-chip

A processor-implemented method for a memory storage format to accelerate machine learning (ML) on a computing device is described. The method includes receiving an image in a first layer storage format of a neural network. The method also includes assigning addresses to image pixels of each of three channels of the first layer storage format for accessing the image pixels in a blocked ML storage acceleration format. The method further includes storing the image pixels in the blocked ML storage acceleration format according to the assigned addresses of the image pixels. The method also includes accelerating inference video processing of the image according to the assigned addresses for the image pixels corresponding to the blocked ML storage acceleration format.

Memory storage format for supporting machine learning acceleration

Growing community of inventors

Bengaluru, India

Sandeep Pande