Nvidia Corporation

Sandeep Navada

Manan Patel

Gentaro Hirota

Jerome Francis Duluk, Jr

Jack H Choquette

Shirish C Gadre

Lacky V Shah

John H Edmondson

Olivier Giroux

Ronny Krashinsky

Luke Durant

Brian S Pharris

Ravi Kiran Manyam

Ze Long

Jeff Tuckey

Apoorv Parle

Wish Gandhi

Prakash Bangalore Prabhakar

Greg Palmer

Rajballav Dash

Steve Heinrich

Eric Werness

Naman Govil

Shayani Deb

Nirmal Raj Saxena

Steven James Heinrich

Naveen Cherukuri

Peter C Mills

Liang Yin

Praveen Joginipally

Vaishali Kulkarni

Adam Hendrickson

David Charles Patrick

Saurabh Hukerikar

Paul Racunas

Yiyang Feng

Abhijeet Ghadge

A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.

Cooperative group arrays

Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache. Such distributed shared memory supports cooperative parallelism and strong scaling across multiple processing cores by permitting data sharing and communications previously possible only within the same processing core.

Distributed shared memory

Various embodiments include a parallel processing computer system that detects memory errors as a memory client loads data from memory and disables the memory client from storing data to memory, thereby reducing the likelihood that the memory error propagates to other memory clients. The memory client initiates a stall sequence, while other memory clients continue to execute instructions and the memory continues to service memory load and store operations. When a memory error is detected, a specific bit pattern is stored in conjunction with the data associated with the memory error. When the data is copied from one memory to another memory, the specific bit pattern is also copied, in order to identify the data as having a memory error.

Error containment for enabling local checkpoint and recovery

Growing community of inventors

San Jose, CA, United States of America

Sandeep Navada