Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

Imec

Sandeep Kumar Goel

Yun-Han Lee

Ankita Patidar

Tze-Chiang Huang

Kai-Yuan Ting

Erik Jan Marinissen

Mohammed Moiz Khan

A non-transitory computer-readable storage medium is encoded with a set of instructions for designing a semiconductor device using electronic system level (ESL) modeling for machine learning applications that, when executed by at least one processor, cause the at least one processor to: retrieve a source code operable to execute a plurality of operations of a machine learning algorithm; classify a first group of the plurality of operations as slow group operations and classify a second group of the plurality of operations as fast group operations, based on a time required to complete each operation; define a neural network operable to execute the slow group operations; define a trained neural network configuration including a plurality of interconnected neurons operable to execute the slow group operations; and generate an ESL platform for evaluating a design of a semiconductor device based on the trained neural network configuration.

System and method for ESL modeling of machine learning

A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit or a burn-in heat distribution across the integrated circuit that includes a set of circuit blocks or a first set of heaters. The integrated circuit design corresponding to the integrated circuit. The performing the simulation includes determining a heat signature of the integrated circuit design from configured power information or location information for each circuit block of the set of circuit blocks or each heater of the set of heaters included in the integrated circuit design. The heat signature includes heat values distributed throughout the integrated circuit design.

Method of testing an integrated circuit and testing system

A method includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group has a unique dominant feature among a plurality of features of the plurality of paths. The method further includes testing a path in a group and, when the path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram. The plurality of features includes a numerical feature having a numerical value, and a categorical feature having a non-numerical value. The non-numerical value is converted into a converted numerical value. The plurality of groups is created based on the numerical value of the numerical feature, and the converted numerical value of the categorical feature.

Integrated circuit design method, system and computer program product

A circuit includes a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit. The circuit includes a second plural number (S) of multiplexers operatively coupled to the scan chain, wherein the S is determined as where the M represents a diagnostic resolution. The multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages.

Scan chains with multi-bit cells and methods for testing the same

A method (of manufacturing a semiconductor device) includes: migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, at least the second netlist being stored on a non-transitory computer-readable medium, the migrating including: generating first versions correspondingly of the first and second netlists; abstracting selected components in the first version of the second netlist and correspondingly in the first version of the second netlist to form corresponding second versions of the second and first netlists; performing a logic equivalence check (LEC) between the second versions of the first and second netlists, thereby identifying migration errors; and revising the second version of the second netlist to reduce the migration errors, thereby resulting in a third version of the second netlist.

Method and system for reducing migration errors

A method includes receiving a source code for executing a plurality of operations associated with a machine learning algorithm, classifying each operation into a fast operation group and/or a slow operation group, defining a neuron network for executing operations of the slow operation group, and mapping the neuron network to an initial machine learning hardware configuration. The method also includes executing the slow operation group operation on the machine learning hardware configuration, finalizing the machine learning hardware configuration capable of successfully executing least one test data set.

A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, manufacturing the integrated circuit according to the integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in heat distribution across the integrated circuit. The integrated circuit design corresponds to the integrated circuit. The integrated circuit is coupled to the test circuit board. The integrated circuit includes a set of circuit blocks and a first set of heaters.

A test circuitry is configured to test for transition delay defects in a first inter-die interconnect connecting a first die and a second die. A test data value is initially received and temporarily stored in a data storage element. The test data is subsequently looped between the storage element and the second die through a feedback loop including the first inter-die interconnect and a second inter-die interconnect. A data conditioner conditions the test data value received from the second die so as to make it distinguishable from the test data value sent to the second die. A clock pulse generator generates a delayed clock pulse. A selection logic applies the generated delayed clock pulse and the conditioned fed back test data value to the data storage element. A readout unit for reading out a test data value stored in the data storage element.

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Hsinchu, Taiwan

Sandeep Kumar Goel