International Business Machines Corporation

Sandeep Korrapati

Kousik Dan

Raja Das

Joji P George

Nitish Jindal

Amarnath Thulabanthula

Sachin Gupta

Santosh Balasubramanian

Holger Horbach

Klaus Keuerleber

Alexander Jung

Juergen Wakunda

Joerg Behrend

Anusha Reddy Rangareddygari

Puli Srivani

Sreekanth Reddy Kadapala

Madhuri Soma

Shakeeb Pasha Bk

Pretty Mariam Jacob

Swathi Priya S

A method, system, and computer program product for parallel regression to bypass regression process interruption are provided. The method identifies an RTL design. The RTL design is converted into a control data flow graph having a plurality of nodes and a plurality of arcs. A mapping table is generated with a machine learning database from a set of test cases based on the control data flow graph. The method selectively calls one or more test cases of the set of test cases to merge a branch to a main repository to bypass a portion of a regression process.

Collateral correlated regression in version control repository

Providing a method and a corresponding system for encrypting customer workload data through a trusted entity such as a self-boot engine (SBE). More specifically, there is a method and a corresponding system for securely extracting out customer centric data in a manner that requires the customer payloads and/or workloads to register with the SBE and share the encryption key.

Securing customer data and internal register data during hardware checkstops in a multi-tenant environment

Validating code that is stored in non-volatile memory. In some instances, code that is written and/or processed by an outside entity that is brought into a local non-volatile memory setting can potentially compromise a given computer system. In order to ensure that this type of code is secure, there are methods to generate interrupt signals that can later be overridden by Otprom code in order to properly validate this outside code.

Validating and securing non-volatile memory

Embodiments include dynamic control of coverage by a verification testbench. Aspects include obtaining a design under test to be verified by the verification testbench and obtaining one or more testcases for execution by the verification testbench on the design under test. Aspects also include obtaining a plurality of triggers corresponding to the design under test, wherein each of the plurality of triggers includes an activation condition, a deactivation condition and a coverage. Aspects further include simulating, by the verification testbench, execution of the one or more testcases by the design under test. Based on detecting the activation condition of one of the plurality of triggers, aspects also include recording, in a coverage database, data specified in the coverage corresponding the one of the plurality of triggers until the deactivation condition is detected.

Dynamic control of coverage by a verification testbench

Embodiments provide a mutable CRTM schema for ensuring the integrity of a client workload on a single system as updates are made to the firmware used to initialize and run that system by booting a computing system in a secure mode; when successfully validating a boot image for the computing system via a secure verification code that is blocked from write access when the system is booted in a unsecure mode, allowing write access to the secure verification code; and continuing to boot the computing system in the secure mode according to the boot image. When booting the system and unseccessfully validating the boot image at the third time, the system boot is failed.

Unsecure to secure transition of mutable core root of trust

A method, system, and computer program product are described for use with graph-based verification of a circuit design. The method comprises performing, using a graph referencing the circuit design, a predefined set of one or more test sequences. The method further comprises determining that a first coverage point of the graph is not fully hit by the predefined set, and back-traversing the graph from a second coverage point of the graph that is partially hit or fully hit by the predefined set. The method further comprises generating, based on back-traversing the graph, a prospective test sequence to fully hit the first coverage point.

Functional coverage enhancement in portable stimulus graphs

Cover points are automatically generated based on analysis of the hardware design represented in register transfer level (RTL) of a hardware description language. A cover point generator uses uncertainty of event occurrence, critical point analysis and redundancy elimination to determine consequential cover points for function verification. A user may provide input parameters to the cover point generator to define depth and width of cover events for generating cover points.

Automatic cover point generation based on register transfer level analysis

Disclosed aspects relate to controlling an electronic circuit having multiple units with at least one signal input each. A set of signal resources is determined by tracing back a dependency tree for each unit signal input until an endpoint representing a signal resource is reached. For each signal resource in the set a resource manager may be provided in dependence of its signal type. That resource manager may be assigned a set of signal inputs comprising each signal input in the circuit which was traced back to its respective signal resource. The resource manager is configured for controlling the signal resource. A control device may be provided to receive technical implementation requirements for one or more of the resource managers, detect conflicting requirements received for the one or more resource managers, and enable or disable one or more of the resource managers in response to the detected conflicting requirements.

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Bengaluru, India

Sandeep Korrapati