Stmicroelectronics International N.v.

Sandeep Kaushik

Paras Garg

Ankit Agrawal

Zubair Khan

Provided are techniques for detecting a short circuit fault at an output of a regulator and protecting the regulator from the short circuit fault. An error amplifier receives a reference voltage and a feedback voltage and compares comparing the reference voltage with the feedback voltage for driving a power transistor of the regulator. A modification stage compares an output voltage of the voltage regulator with a fault reference voltage and in response to determining that the output voltage of the voltage regulator is less than the fault reference voltage, drives the power transistor using an internal node of the error amplifier by changing states of a first switch and a second switch and supplies the reference voltage to both the first and second inputs of the error amplifier by changing states of a third switch and a fourth switch.

Short circuit fault protection for a regulator

A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

Low-voltage differential signaling (LVDS) transmitter circuit

Low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods are provided. A LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor.

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Greater Noida, India

Sandeep Kaushik