Intel Corporation

Sandeep K Jain

Animesh Mishra

Jun Shi

David Wyatt

John B Halbert

Melik Isbara

Kuljit Singh Bains

James P Kardach

George Vergis

Andrew M Volk

Bill Nale

Howard S David

Udayan Mukherjee

Pochang Hsu

Jim Kardach

Thomas Dean Skelton

Methods, systems, and storage media for image thresholding at a network edge device are disclosed herein. In an embodiment, a network edge device may include a camera to be operated by at least one of the one or more processors to capture a monitoring image of a condition proximal to the device at a location. An image threshold module may be operated by at least one of the one or more processors to determine if the monitoring image exceeds a threshold relating to the condition at the location. A communication module may communicate to a remote network location an indication if the monitoring image exceeds the threshold relating to the condition.

Network edge device with image thresholding

An agricultural data collection system may include a plurality of self-powered agricultural data collection devices disposed across an agricultural area. The agricultural data collection system may also include a plurality of self-powered agricultural output devices that control the distribution of one or more agricultural resources across at least a portion of the agricultural area. The plurality of self-powered agricultural data collection devices and the plurality of self-powered agricultural output devices may communicate wirelessly to selectively implement an agricultural management method that uses data collected by the self-powered agricultural data collection devices to provide agricultural resources where needed within localized agricultural areas within a larger agricultural area. At times, the agricultural management method may include an adaptive method that employs machine learning principles to optimize agricultural production within the agricultural area.

Intelligent agricultural systems

A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.

Method, apparatus, and system for active refresh management

In one embodiment, the present invention includes a method determining if an access queue associated with a channel of a memory has been empty for a predetermined time period and if so, de-asserting a clock enable signal for all ranks of the channel of the memory, otherwise providing a next memory access request from the access queue to the channel of the memory. Other embodiments are described and claimed.

Coarsely controlling memory power states

Systems and methods of managing memory provide for detecting a request to activate a memory portion that is limited in size to a partial page size, where the partial page size is less than a full page size associated with the memory. In one embodiment, detecting the request may include identifying a row address and partial page address associated with the request, where the partial page address indicates that the memory portion is to be limited to the partial page size.

Partial page scheme for memory technologies

Data regarding physical parameters and security and commands to send such data can be communicated between a memory device and a memory controller using a memory bus connected between the two. In one embodiment, the invention includes receiving a first command at a memory device on a memory bus, the first command being other than a read or write command, and receiving a second command together with the first command, the second command to be initiated using lines that are not used by the first command.

Memory device commands

A method, apparatus, and system are described in which a memory controller may have two or more registers to create and track zones of memory in a volatile memory device. The memory controller controls a power consumption state of a first zone of memory in the volatile memory device and a second zone of memory within the first volatile memory device on an individual basis; and one or more memory arrays contained within the first volatile memory device.

Various apparatuses and methods for reduced power states in system memory

The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board, each chip containing a plurality of memory cells and a thermal sensor, and a multiplexer on the printed circuit board, independent of the memory chips, coupled to each of the thermal sensors. A current source is coupled to the multiplexer to provide a current to each one of the thermal sensors, and a voltage detector is coupled to the multiplexer to detect a voltage from each of the thermal sensors when a current is applied. A temperature circuit is coupled to the voltage detector to determine a temperature for each memory chip based on the detected voltage.

Temperature determination and communication for multiple devices of a memory module

In one embodiment, a method is provided. The method comprises upon entering a self-refresh mode, refreshing memory cells in a memory device at a first refresh frequency; and upon a predefined event refreshing the memory cells at a second refresh frequency, while in the self-refresh mode.

Method and apparatus to control a power consumption of a memory device

A thermal management system is described which may be implemented on a semiconductor die. The system may include a thermal sensor thermally coupled to the die to sense the temperature of the die and generate an output representing the sensed temperature, and an adjustable compensation circuit coupled to the thermal sensor to compensate the thermal sensor output. The adjustable compensation circuit may be applied to the thermal sensor or to a threshold.

Calibration of thermal sensors for semiconductor dies

Thermal management and communication is described in the context of memory modules that contain several memory devices. In one example, the invention includes determining a temperature of a first memory device, the first memory device containing a plurality of memory cells, determining a temperature of a second memory device after determining the temperature of the first memory device, the second memory device containing a plurality of memory cells, and generating an alarm based on an evaluation of the first and the second temperatures. In another example, the invention includes detecting a thermal event on a memory device of a memory module that contains a plurality of memory devices, detecting the state of an event bus of the memory module, and sending an alert on the event bus if the event bus is in an unoccupied state.

In one embodiment, a method includes periodically charging a capacitor mounted on an electronic component; initializing a timer to count down from a counter value, once the capacitor is charged; determining if the capacitor has discharged before the timer has counted down to zero; and if the capacitor has discharged before the timer has counted down to zero then generating an interrupt.

Method and apparatus to implement a temperature control mechanism on a memory device

In one embodiment a memory controller is provided. The memory controller comprises a predictive logic circuit to predict an increase in a current operating temperature of a memory device coupled to the memory controller, based on memory cycles to be issued to the memory device; and a temperature control circuit to perform a temperature control operation wherein if the sum of the current operating temperature and the predicted increase in temperature is greater than a threshold temperature associated with the memory device, then the number of memory cycles issued to the memory device is reduced.

Method and apparatus to control the temperature of a memory device

A method and apparatus is disclosed for reducing ringing of a digital signal delivered over a transmission line. A clamping circuit implemented in accordance with one embodiment of the invention includes a delay circuit. The delay circuit receives an input signal delivered over a transmission line and delivers a second signal after a preselected delay. A driver circuit receives the second signal and the input signal and provides an enable signal to a transistor for a period of time corresponding to the preselected delay. The transistor is coupled between a supply voltage and the transmission line. An inverter having an input and an output is also included, with the input of the inverter electrically connected to the transmission line. An additional transistor is electrically coupled between the supply voltage and the transmission line. The additional transistor has an enable input that is electrically connected to the output of the inverter to enable the additional transistor when the inverter outputs a predetermined voltage level.

Growing community of inventors

Milpitas, CA, United States of America

Sandeep K Jain