Sun Microsystems, Inc.

Sandeep K Aggarwal

Gunes Aybay

Marc E Levitt

David A Penry

Srinivas Nori

David F Bertucci

A CPU includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU includes a decode stage, an arbitration stage, and a control stage. Incoming requests asserted by the CPU module unit are provided to the BIU decode stage which, in response thereto, determines the type of transaction requested, the initiator module unit, and the target module unit. If the target identified in the decoded request is ready to accept a command, the decode stage forwards the request to the arbitration stage. The arbitration stage arbritrates amoung the present requests asserted by the module units and, in response thereto, alerts the control stage as to which of the module units has won the arbitration. The control stage decodes the request corresponding to the module unit that won the arbitration to determine the transaction type and target unit. The control stage selects within appropriate address and data multiplexers those inputs corresponding to the initiator and target units identified in the request. In this manner, the dedicated buses between the initiator unit and the BIU are effectively coupled to the common bus so as to allow for the transmission of information from the initiator unit to the target unit via the BIU.

Apparatus and method for controlling data, address, and enable buses

Requests from CPU module units are arbitrated according to a two-level priority scheme, the first level being of a higher priority than the second level. The first level includes a specific CPU module unit, and the second level includes a predetermined sequence of values corresponding to the remaining CPU module units. During each arbitration cycle, a request from the first level CPU module is automatically granted. If the first level CPU module unit has not asserted a request, requests from the second level module units are arbitrated according to the above-mentioned predetermined sequence. The sequence value corresponding to the second level CPU module whose request was most recently granted is latched. Arbitration is then granted to the module unit corresponding to the sequence value which follows the latched value. If the corresponding module unit has not asserted a request, then arbitration is granted to the module unit corresponding to the next value in the predetermined sequence, and so on, unit all of the module units assigned to the second priority level are polled. If no requests have been asserted by the second level module units, arbitration defaults to the first level module unit.

Apparatus and method for arbitrating transactions requiring multiple

A CPU of a microprocessor includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU has a plurality of first ports coupled to respective first ports of the module units via dedicated buses therebetween and has a second port coupled to a first port of the common bus. The module units each include a second port coupled to respective second ports of the common bus. Communication between the module units is routed through and controlled by the BIU. To request a transaction, a module unit (the initiator) sends a request to the BIU via its dedicated bus to the BIU. The BIU arbitrates among present requests and, in response thereto, grants the arbitration winner's request and transmits a command to the target of the requested transaction. Preferably, both of these signals being are transmitted via the dedicated buses. Thereafter, data is routed from, for instance, the target, to the BIU via a corresponding dedicated bus. The BIU then routes the data to the initiator via the common bus.

High speed modular internal microprocessor bus system

A circuit is disclosed which allows an IN-Test to be performed on an integrated circuit (IC) without having to stop the external clock sources by disabling the IC's internal phase-locked loops. Information indicative of the IC's clock mode and of the desired stop mode is contained within the IC's clock control register. In one embodiment, the internal clocks may be stopped in either of three stop modes while operating in one of three clock modes. When it is desired to stop the IC's internal clocks, the clock control register provides a stop instruction signal STOP.sub.-- INSTR to a clock control circuit which, depending upon the particular stop mode and clock mode encoded in signal STOP.sub.-- INSTR by the clock control register, asserts a enabling signal to a disable clock circuit. In response to this active-high enabling signal, the disable clock circuit asserts a zero feedback signal to the internal phase-locked loops of the IC and thereby forces the voltage controlled oscillators within the phase-locked loops to hold internal clocks low. In this manner, the IC internal clocks may be stopped to allow a test vector to be scanned out of the IC during an IN-Test without stopping the external clock source.

Clock stopping schemes for data buffer

Circuits and methods of testing an integrated circuit die are disclosed. Active logic setting circuits are incorporated into input cells of a die. During testing, the active logic setting circuits weakly drive the input cells to a definite logic level. Therefore, the necessity of connecting probes to all of the input pads to prevent floating signals in the die is eliminated. Furthermore, during normal operations the active logic setting circuits have little or no effect on the performance of the die.

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Santa Cruz, CA, United States of America

Sandeep K Aggarwal