Xilinx, Inc.

Sandeep Jayant Sathe

Vamsi Krishna Nalluri

Sai Lalith Chaitanya Ambatipudi

Chaithanya Dudha

Mrinal J Sarmah

Rajeev Patwari

Shreyas Manjunath

Krishna Kishore Bhagavatula

Approaches for data compression involve a compression circuit packing non-zero data elements of a succession of words of a plurality of blocks into packed words by packing non-zero data elements of one or more words of the succession in each packed word, and restricting each packed word to data elements of one uncompressed block. The compression circuit writes each packed word in a RAM and within a compressed address range associated with the uncompressed block when the packed word is full of non-zero data elements, or before the packed word is full if the next input word is of another uncompressed block.

Compression of sparse tensors

An electronic system includes a mapping circuit configured to receive input samples of a dataset within a defined range of values. The mapping circuit is configured to perform comparisons that compare each input sample to each of a plurality of comparison values selected from the defined range of values. For each comparison, the mapping circuit generates an indication value specifying whether the input sample used in the comparison is greater than or equal to the comparison value used in the comparison. The system includes an adder circuit configured to generate a sum of the indication values for each comparison value and a memory configured to maintain counts corresponding to the comparison values. The counts are updated by the respective sums. The system includes a threshold detection circuit configured to determine, for the dataset, a threshold value or threshold range based on the counts read from the memory.

Circuit architecture for determining threshold ranges and values of a dataset

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Pune, India

Sandeep Jayant Sathe