Globalfoundries Inc.

Sandeep Gaan

Huang Liu

Sipeng Gu

Zhiguo Sun

Shishir K Ray

Guillaume Bouche

Haigou Huang

Jin Ping Liu

Xiang Hu

Hongliang Shen

Changyong Xiao

Seung Yeon Kim

Hsin-Neng Tai

Weihua Tong

Sang Cheol Han

Tae Hoon Kim

Ja Hyung Han

Jerome F Wandell

Kyutae Na

Andy C Wei

Andy Chih-Hung Wei

Huy Cao

Edmund Kenneth Banghart

Xinyuan Dou

Sukwon Hong

Hoong Shing Wong

Songkram Srivathanakul

Tao Han

Wen-Pin Peng

Sheldon Meyers

Shimpei Yamaguchi

Yiqun Liu

Danni Chen

Adam Selsley

Satyajit Shinde

Carlos Chacon

Fabio D'Addamio

Nisha Pillai

Kyle Jung

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200&#xb0; C. with a process gas including Nand HO.

Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing

Provided is a semiconductor device that includes a semiconductor substrate and a 10 to 40 &#x212b; thick high-k dielectric layer that contains one or both of hafnium dioxide (HfO) and zirconium dioxide (ZrO). The high-k dielectric layer is disposed on the semiconductor substrate, and it contains at least some tetragonal phase HfOand/or tetragonal phase ZrO. Also provided are methods for making the semiconductor device, and electronic devices that employ the semiconductor device.

Devices comprising high-K dielectric layer and methods of forming same

Semiconductor substrates and methods for processing semiconductor substrates are provided. A method for processing a semiconductor substrate includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.

Semiconductor substrates and methods for processing semiconductor substrates

Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

FinFET devices comprising a dielectric layer/CMP stop layer/hardmask/etch stop layer/gap-fill material stack

Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.

Inhibiting diffusion of elements between material layers of a layered circuit structure

Processes for preparing an integrated circuit for contact landing, processes for fabricating an integrated circuit, and integrated circuits prepared according to these processes are provided herein. An exemplary process for preparing an integrated circuit for contact landing includes providing a semiconductor structure that includes a transistor with source and drain regions, wherein at least one of the source and drain regions has a shaped contact structure overlaid with a contact etch stop layer and a pre-metal dielectric material. The pre-metal dielectric material is removed with one or more anisotropic etches, including at least one anisotropic etch selective to the pre-metal dielectric material. And, the contact etch stop layer overlaying the shaped contact structure is removed with a third anisotropic etch selective to the contact etch stop layer material to expose the shaped contact structure.

Processes for preparing integrated circuits with improved source/drain contact structures and integrated circuits prepared according to such processes

Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a 'buffer zone' or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Shallow trench isolation integration methods and devices formed thereby

Patterning multiple, dense features in a semiconductor device using a memorization layer

Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.

Semiconductor structures with bridging films and methods of fabrication

Circuit structure fabrication methods are provided which include: providing an interlayer structure above a substrate, the interlayer structure including porogens dispersed within a dielectric material; and pulse laser annealing the interlayer structure to form a treated interlayer structure, the pulse laser annealing polymerizing the dielectric material of the interlayer structure to form a polymeric dielectric material, that includes pores disposed therein. The pulse laser annealing facilitates increasing elasticity modulus of the treated interlayer structure by, in part, maintaining structural integrity of the treated interlayer structure, notwithstanding that there are pores disposed within the polymeric dielectric material which, for instance, facilitates reducing dielectric constant of the treated interlayer structure.

Method of fabricating an interlayer structure of increased elasticity modulus

A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

Methods for fabricating integrated circuits utilizing silicon nitride layers

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Clifton Park, NY, United States of America

Sandeep Gaan