Texas Instruments Corporation

Sanchayan Sinha

Dharin Nayeshbhai Shah

Achin Grover

Amitabha Banerjee

Pranab Ghosh

A memory cell supporting scan-based tests and with reduced time delay in functional mode. The memory cell generates separate clocks for latching functional and scan data into a storage element contained in the memory cell. The use of separate clock signals permits transmission of scan data and functional data via separate paths, thereby eliminating additional circuitry that are otherwise needed to multiplex such scan and functional data through a same path. The absence of such additional circuitry reduces the time delays from input to output. The structure of the memory cell provided also permits easy addition of logic functions without substantially affecting operating speeds.

Cell supporting scan-based tests and with reduced time delay in functional mode

A synchronizer circuit which synchronizes an input clock signal to a sampling clock to generate a synchronized signal. In an embodiment, an adaptive module detects the occurrence of a positive edge in an input clock signal after a logic low corresponding to a prior negative edge is propagated to as a synchronized signal, and provides a logic high as an input to a sampling module. The sampling module propagates the signal led at the input as the synchronized signal. The adaptive module causing the input to remain at logic high at least until the synchronization module provides logic level as the synchronized signal. The negative edges in the input signal may also be processed similarly.

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Bengaluru, India

Sanchayan Sinha