Intel Corporation

Sanaz Kabehie

Robert S Chau

Marko Radosavljevic

Niloy Mukherjee

Niti Goel

Gilbert W Dewey

Ravi Pillarisetty

Matthew V Metz

Han Wui Then

Sansaptak W Dasgupta

Rafael Rios

Seung Hoon Sung

Annalisa Cappellani

Cory E Weber

Martin D Giles

Aaron A Budrevich

A die includes a semiconductive prominence and a surface-doped structure on the prominence. The surface-doped structure makes contact with contact metallization. The prominence may be a source- or drain contact for a transistor. Processes of making the surface-doped structure include wet-vapor- and implantation techniques, and include annealing techniques to drive in the surface doping to only near-surface depths in the semiconductive prominence.

Methods to enhance doping concentration in near-surface layers of semiconductors and methods of making same

Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.

Semiconductor device having metallic source and drain regions

Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation

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Portland, OR, United States of America

Sanaz Kabehie