Ntt Mobile Communications Network, Inc.

Ntt Docomo, Inc.

Ntt Mobile Communications

Sanae Hotani

Takashi Suzuki

Toshio Miki

Toshiro Kawahara

Toshirou Kawahara

The writing address supply partsupplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory. The reading address supply partalternately supplies to the operating memorya plurality of addresses for reading a plurality of continuous bits corresponding to the header H from the operating memory, and an address for reading 1 bit corresponding to the data D from the operating memory, and reads the bit sequence such that the bits forming the bit sequence corresponding to the header H are scattered and arranged within the bit sequence forming the data D, from the operating memory. In accordance with such an interleaving device, it is possible to individually randomize frames according to their constituent data, and it is possible to transmit the bits that make up such data in a format which is most suited for said data.

Method and device for interleaving and method and device for de-interleaving

Method and device for interleaving and method and device for deinterleaving

In a frame synchronization circuit, which prevents the occurrence of synchronous error due to a data loss/insertion while restraining a false synchronization/out of synchronization based on typical code error in a conventional data transmission system, the frame synchronization circuit is provided with a frame synchronization code detector which detects a frame synchronization code from a received data sequence to output a frame position and outputs a checked result by checking a frame synchronization code detected and a correct frame synchronization code. The frame synchronization circuit is also provided with and a data loss and data insertion period judgment circuit which determines which presumes whether a data loss or data insertion has occurred in the received data sequence according to the checked result.

Frame synchronization circuit

The frame-forming data computing part sorts a plurality of types of parameters forming the frames, and generates frame-forming data that contains data relating to the configuration of said frames and data establishing for each class the error protection method to be applied to each said parameter. The frame-forming data error protection processing part implements the specified error protection for said frame-forming data. The class data error protection processing part implements error protection that is specified for each class according to the frame-forming data, with respect to the parameters that are sorted into a plurality of classes. The synthesizer transmits the frame-forming data that has undergone the specified error protection and the parameters that have undergone the error protection established for each class. In accordance with the present invention, error correction is implemented on frame-forming data indicating the configuration of the frames, and it is also implemented on each class according to the frame-forming data, and these two are synthesized and output. Therefore, it becomes possible to obtain data relating to the configuration of said frames, according to frame-forming data received by the receiving side device. As a result, it is possible to set on the transmission side as desired the content of the error protection to be applied to each class, and in addition, error protection becomes possible for each frame, due to the fact that these data are contained in the frame-forming data, even if the frame has a variable frame length, with the number of bits fluctuating over time.

Error protection method and error protection device

Likelihood calculating circuit A1 calculates the hamming distance between a received data series and a unique word as likelihood data d1. Likelihood calculating circuit A2 calculates the number of transmission errors using redundant data, and outputs this value as likelihood data d2. Likelihood data d1,d2 are added at adding circuit 21, and the output thereof is compared to the threshold value of determination circuit with threshold 22. The results of this comparison are output as determination signal with threshold DT. Synchronous determination circuit 23 generates a synchronous determination signal SD based on determination signal with threshold DT. Accordingly, the present invention provides a frame synchronization circuit in which it is possible to avoid out of synchronization or false synchronization, without increasing the amount of redundancy necessary to detect frame synchronization.

Growing community of inventors

Kanagawa, Japan

Sanae Hotani