Kabushiki Kaisha Toshiba

Sanae Fukuda

Takahisa Kanemura

Masao Iwase

Naoyuki Shigyo

Makoto Yoshimi

Hirotaka Amakawa

Process simulation for LSIs and other semiconductor devices will handle plural same impurities introduced in different processes as different impurities. Thus, by handling them as different impurities in calculation, it is possible to obtain the distribution profiles of impurities in semiconductor devices without being effected by another same impurity introduced in another process or a number of processes during processing. With this, even a plurality of process conditions are discussed or when one or some of process(es) in a sequence of semiconductor device fabrication processes is (are) changed in procedure, it is not necessary to repeat the process simulation many times from the beginning. And it is possible to easily decide which process must be changed in conditions based on a finally obtained structure of semiconductor devices. The process simulation results are used directly as input to device simulation, to rapidly obtain performance of semiconductor devices such as current vs voltage characteristics. Therefore, the efficiency of calculations required to obtain the optimal conditions for semiconductor structures can be improved, thus shortening the lapse of time for designing and development of semiconductor devices.

Method and apparatus for obtaining structure of semiconductor devices

A MOSFET comprises a silicon substrate 1 having a source/drain region 7b formed in a surface region thereof, an insulating film 3 formed of silicon oxide, and a gate electrode 4a. The side surface region of the electrode 4a is covered with an insulating film 6 formed of silicon nitride. The insulating film 6 has an extended portion interposed between the electrode 4a and the insulating film 3 in a manner to surround the lower corner portion 4b of the electrode. Since the insulating film 6 has a dielectric constant larger than that of the insulating film 3, it is possible to suppress the electric field intensity at the lower corner portion 4b of the electrode.

Semiconductor devices having an improved gate

A CMOS inverter circuit incorporating a P channel MOSFET and an N channel MOSFET, both of which can achieve surface conduction, is provided while maintaining the prescribed miniaturization. Thus, the threshold value and conductance of the both MOSFETs are independent of the thickness of the silicon film, and can be easily controlled in the manufacturing processes thereof.

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Tokyo, Japan

Sanae Fukuda