Apple Inc.

Azul Systems, Inc.

Samy R Makar

Anuja Banerjee

Santiago Fernandez-Gomez

Vijay M Bettada

Anh T Hoang

Jianlin Yu

Ravi Karapatti Ramaswami

Niteen A Patkar

A method and apparatus for conducting a transition test of a source synchronous interface is disclosed. A system includes a source synchronous transmitter and source synchronous receiver. The source synchronous transmitter includes a first scannable flop having an output coupled to a data input of a second scannable flop in the source synchronous receiver. During a transition test, the source synchronous transmitter is configured to transmit data from the first scannable flop to the second scannable flop, along with a clock signal at an operational clock speed. The first scannable flop is coupled to feedback circuitry configured to cause transitions of the transmitted data. The second scannable flop may capture the transmitted data. The captured data may be subsequently used to determine if the desired transitions were detected by the second scannable flop.

Transition fault testing of source synchronous interface

A method and apparatus for detecting clock glitches during at-speed testing of integrated circuits is disclosed. In one embodiment, an integrated circuit includes a scan chain having a number of scan elements coupled in a series configuration. Each of the scan elements is coupled to receive a clock signal that may be cycled during a test operation. A subset of the scan elements are arranged to form, along with other components, a counter. Test stimulus data shifted into the scan chain to perform a test may include an initial count value that is shifted into the scan elements of the counter. When the test is performed, the count value is updated responsive to cycling of the clock signal. The updated count value is shifted from the counter along with other test result data, and may be used to determine if the number of clock cycles received during the test.

Apparatus and method for clock glitch detection during at-speed testing

An apparatus and method for protecting the contents of a secure register from scan accessibility is disclosed. The secure register may include a number of scannable elements within a scan chain. During a normal scan test mode, the scannable elements of the secure register may be accessibly, as data may be shifted to, from, or through these elements. During certain other modes (e.g., a scan dump or memory dump), a bypass circuit may be invoked to effectively separate the scan elements associated with the secure register from the remainder of the scan chain. During operation in one of these modes, no data may be shifted to, from, or through the scan elements of the secure register. Accordingly, the bypass path may protect secure data stored in the secure register from unauthorized access.

Secure register scan bypass

A method and apparatus for dynamic scan chain grouping is disclosed. In one embodiment, an integrated circuit (IC) includes a number of scan partitions. Each scan partition includes a number of scan input ports and a number of corresponding scan output ports. Each scan input port and each scan output port includes a number of scan paths. Additionally, each scan partition includes a number of scan chains. Each scan partition is programmable to couple the scan paths of one of the scan input ports to each of the scan chains. Similarly, the corresponding output port may also be coupled to the scan chains. The scan paths of the remaining scan input ports may be selected to bypass the scan chains of the scan partition, having their respective scan input ports connected directly to their respective scan output ports. Each scan partition may be reconfigurable.

Dynamic scan chain grouping

A multi-processor chip has several processor cores that are simultaneously tested in parallel. The processor cores each have identical scan chains that produce identical test results absent defects. Expected test data is scanned from an external tester onto the chip and replicated to each processor core's scan chain. The expected test data is compared to scan chain outputs at each processor core. Any mismatches set a test-fail bit for that processor core. Each processor core has repairable scan chains and a separate critical scan chain. Failures in the critical scan chain in any processor core cause the whole chip to fail. Processor cores are disabled that have failures in their repairable scan chains, allowing the chip to be repairable by using the remaining processor cores. Critical scan chains include logic that drives to other blocks on the chip, while repairable scan chains have logic embedded deep within a processor core.

Testing replicated sub-systems in a yield-enhancing chip-test environment using on-chip compare to expected results for parallel scan chains testing critical and repairable sections of each sub-system

Growing community of inventors

Fremont, CA, United States of America

Samy R Makar