International Business Machines Corporation

Samsung Display Co., Ltd.

Samuel Taylor Ray

Hayden C Cranford, Jr

Louis Lu-Chen Hsu

Vernon Roberts Norman

James Stephen Mason

Stacy J Garvin

Gareth John Nicholls

Philip J Murfet

Shashikala Govindu

Carl Christopher Hanke, Iii

Wayne A Utter

A voltage regulator that includes a first amplifier, a second amplifier, a summer, and a transistor is presented. The first amplifier has a first gain and a first frequency bandwidth, and is configured to generate a first voltage output. The second amplifier has a second gain that is lower than the first gain and a second frequency bandwidth that is higher than the first frequency bandwidth, and is configured to generate a second voltage output. The summer is configured to generate a summed voltage output. The transistor is connected to the summer and configured to generate a regulated voltage based on the summed voltage output of the summer.

Dual loop voltage regulator utilizing gain and phase shaping

A voltage regulator includes a first amplifier having a first gain and a first frequency bandwidth, and generating a first voltage output; a second amplifier having a second gain that is lower than the first gain and a second frequency bandwidth that is higher than the first frequency bandwidth, and generating a second voltage output; a summer generating a summed voltage output based on the first voltage output and the second voltage output; and a transistor connected to the summer and generating a regulated voltage based on the summed voltage output of the summer.

A method and current mode logic (CML) multiplexer circuit for implementing load balancing, and a design structure on which the subject circuit resides are provided. CML multiplexer circuit includes first and second differential transistor pairs receiving a first differential input signal and a second differential input signal. The respective transistors of the first and second differential transistor pairs are connected to respective differential signal first and second outputs. CML multiplexer circuit includes load balancing third and fourth differential transistor pairs receiving the first differential input signal and the second differential input signal. The respective transistors of the load balancing third and fourth differential transistor pairs are connected to the opposite differential signal outputs as the first and second differential transistor pairs and the select devices are turned off, matching the source impedance of the unselected first or second differential transistor pair.

Implementing CML multiplexer load balancing

A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.

Method and system for high frequency clock signal gating

Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.

Electronic component value trimming systems

An SCSI circuit which allows for the independent control of driver slew rate and amplitude with a linear shaped driver output voltage. The circuit comprises 1) a symmetrical H-Driver having at least four predrive controls; and 2) a predrive control circuit coupled to one of the predrive controls for independently varying the amplitude and rise time. The SCSI circuit is designed to utilize minimal space on the IO circuit pad, thereby conserving the amount of space allotted by the silicon area on the integrated circuit chip.

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Morgan Hill, CA, United States of America

Samuel Taylor Ray