International Business Machines Corporation

Samuel Steven Allison

Kenneth James Barker

Joseph Kinman Lee

Steven Howard Johnson

Fabrice Jean Verplanken

Jean Louis Calvignac

Michael Steven Siegel

Marco C Heddes

Brian Mitchell Bass

Anthony Matteo Gallo

A system and method of altering frames being processed by a network processing unit. The system includes a set of defined alterations, with some of the alterations being fixed alterations which are advantageously handled by hardware to accomplish the fixed alterations rapidly and without executing a stored program and other alterations which include a variable portion, with these variable alterations being accomplished through the use of stored programs allowing the variables to be used to effect variable alterations to a frame. The present system accommodates a change in the duration of life of a frame or information unit and addition or deletion of bits and also allows for a new cyclic redundancy checking to be accomplished for a revised information unit. Advantageously, the frame alteration system is on the same substrate as the processors.

Method and system for making a frame alteration in a network processing system

Stations in a communications network are awakened by matching a pattern received from the communications network with patterns in the stations. When a match occurs, the stations are awakened. The patterns are arranged contiguously on word boundaries. A nibble (4 bits) in a mask word identifies the part of the pattern word to be used in the comparison.

Pattern matching in communications network where first memory stores set of patterns, and second memory stores mask data identifying patterns in the first memory

An architecture and NIC (Network Interface Card) for coupling Data Processing Equipment to a communications network includes a host memory having a High Priority Queue storing control information and data, a Low Priority Queue storing control information and data. Control registers, in the NIC, store addresses identifying the location of said Queues and a block size register, in the NIC, stores a value representing the size of data blocks to be transferred from the host memory to the NIC. A controller transfers allowable block size data from the host memory to buffers on said NIC.

Architecture and apparatus for implementing 100 MBPS and GBPS ethernet address

Architecture and apparatus for implementing 100 Mbps and GBPS Ethernet adapters

A multi-port adapter having a single MAC chip has reduced logic circuits for transferring data between a host system and a TDM communication system. The MAC chip includes a transmit MAC and a receive MAC, each coupled at one end to a port multiplexer through an interface and at the other end to respective storage registers. The port multiplexer is coupled to the Physical Layer of each port. Transmit and receive state registers track the state of each port in the transfer of data in the transmit and receive directions. The storage registers are coupled through a host bus interface to a host bus and to the host system. Control logic is coupled to the storage register to control the transfer of data between the system and the storage registers. A port selector coupled between the multiplexer and the transmit and receive state registers selects ports for transfer of data in succession. On each chip clock cycle, the port selector selects a state machine register to determine the state of the MACs for processing the data and a section of the FIFO's to write or read data for the selected port. At the end of the cycle, the state registers are set and stay set until selected again. The process repeats for each port in a cyclic manner. Once data is accumulated in the receive storage register, control logic reads the data of the host bus. Once space is available in the transmit storage register, the control logic writes data from the host system to the transmit storage register.

Architecture for a multi-port adapter with a single media access control (MAC)

Methods, systems or apparatus and computer program products are provided that interface between two data buses operating at different speeds. Such interfaces utilize a buffer which has an apparent size larger than the physical size of the buffer to receive blocks of data which are larger than the size of the buffer. The apparent size of the buffer is created by simultaneously writing data to and reading data from the buffer such that the same storage locations may be used more than once to hold the data. The present invention may be utilized for receiving data from either the high speed or the lower speed bus.

Phantom buffer for interfacing between buses of differing speeds

A multiple port adapter having a single MAC chip with a single I/O port has reduced logic circuits and I/O pins for transferring data between a host system and a TDM communication system. The MAC chip includes a transmit MAC and a receive MAC, each coupled at one end through the single I/O port to a port multiplexer and at the other end to respective storage registers. The port multiplexer is coupled to each port. Transmit and receive state registers track the state of each port in the transfer of data in the transmit and receive directions through the single I/O port. The storage registers are coupled through a host bus interface to a host bus and to the host system. Control logic is coupled to the storage register to control the transfer of data between the system and the storage registers. A port selector coupled between the multiplexer and the transmit and receive state registers selects ports for transfer of data in succession. On each chip clock cycle, the port selector selects a state machine register to determine the state of the MACs for processing the data and a section of the FIFO's to write or read data for the selected port. At the end of the cycle, the state registers are set and stay set until selected again. The process repeats for each port in a cyclic manner. Once data is accumulated in the receive storage register, control logic reads the data of the host bus. Once space is available in the transmit storage register, the control logic writes data from the host system to the transmit storage register.

Architecture for a multiple port adapter having a single media access control (MAC) with a single I/O port

A detector and method for detecting Wakeup-On-LAN (WOL) frames in which the Wakeup field can start on a two byte word boundary (even) or in the middle of the two byte word (odd). The orientation (even/odd) of the WOL and destination address (DA) fields are determined and a first or second two byte process, depending on the orientation, is selected to analyze the frame to determine if it is valid.

Dual two byte process for fast wake-up-on LAN frame detection

A system and method to avoid transmit underruns from a host system to a communication network using an adjustable threshold on a frame basis. The host system includes a device driver, host descriptors and host buffer. The host descriptor define the number of blocks of data to be transferred from the host to the network via a Media Access Control (MAC) device. The MAC device includes a processor, a transmit storage device, and a medium independent interface coupled to the network. The MAC device is connected to the host system via a data bus. A host descriptor is generated for each frame of data transferred by the MAC device from the host to the network. The descriptor is generated by the device driver and provides the MAC processor with a block size of data to be transferred and a threshold in each frame indicating the number of blocks of data to be transferred from the host system to the MAC device to avoid an underrun before transmission to the communication network. The MAC processor generates and transmits a 'retry' bit to the device driver when a transmit underrun occurs. The device driver modifies the threshold in subsequent frames to avoid transmit underruns by raising or lowering the thresholds according to the number of retries.

System and method for avoiding host transmit underruns in a

In a local area network, a system and a method to detect transmit underruns and retransmit frames between a sending station and a receiving station using a Media Access Control (MAC) device in lieu of a sending processor. The MAC device includes a MAC processor for transmitting data in blocks from a host buffer to a storage device, e.g., RAM for retransmission to the network via a Media Independent Interface (MII) unit. The MAC device includes a transmit logic unit which uses a control word set by the MAC processor to transmit data by frames from the storage device to the network. The transmit logic unit includes pointer control logic to identify the start address of the data and to track the data as read from the storage device to the network. When a transmit underrun occurs, the transmit logic recognizes the condition and resets the pointer logic to the start of the first frame for retransmission to the receiving station. During retransmission, the MAC processor continues to transfer data from the sending system to the storage device which eventually provides sufficient data to overcome the underrun condition. A frame is repeated if a underrun condition continues until the frame is transmitted without an underrun condition which eliminates the retransmission request of the receiving station to the sending station. The MAC device enables underruns to be transparent to the sending and receiving station.

Growing community of inventors

Fuquay-Varina, NC, United States of America

Samuel Steven Allison