International Business Machines Corporation

Samuel R Levine

Arnold Weinberger

Richard R Konian

John M Angiulli

Arun K Ghose

David Meltzer

Leon L Wu

Shanker Singh

David T Shen

Kevin P Moran

Wen-Yuan Wang

Vincent C Vasile

Leonard L Fogell

Robert C Letteney

A variable frequency digital ring oscillator which can be formed in a small area for use in testing of chips employs a ring oscillator formed of CMOS inverters, transmission gates and capacitors and CMOS logic as a voltage controlled ring oscillator. A wide range of frequency of oscillation is achieved with small number of components. The ring oscillator circuit's oscillator frequency is controlled only by DC voltages, such as may be provided by (but not limited to) a manufacturing chip tester. The output signal of the oscillator swings between Vdd and Vss and does not need additional level translation circuits to drive CMOS logic. The ring oscillator can be composed of an odd number of CMOS inverters connected in cascade to form a loop. We provide a CMOS transmission gate with PMOS and NMOS transistor device inserted between each adjacent inverter and a MOS capacitor connected between the output of each transmission gate and the Vss supply of the ring oscillator circuit (conventionally ground). The gate voltages of the PMOS and NMOS transistors in the transmission gate are different and provide a different DC voltage between Vdd and Vss. Variation of the gate voltages of the transmission gates controls the frequency of oscillation of the circuit. The use of a plurality of cascaded delay elements between inverters achieves a wider range of oscillation frequency than possible with a single delay element.

CMOS voltage controlled ring oscillator

A low temperature conduction module comprising a cold plate having recesses around the periphery thereof to accommodate memory cubes is disclosed. The recesses accommodating the memory cubes are of such depth and dimension as to enclose the memory cube on all but one side, thereby greatly enhancing the conduction of the heat generated by the memory cube to the cold plate. The memory cube may be surrounded by a material which possesses excellent thermal conductive properties to insure efficient transfer of the heat from the memory cube to the cold plate. The plurality of memory cubes so positioned within the cold plate may be connected by a flexible cable surrounding the cold plate and having branch conductors extending to connect with computer processors enclosed within the same low temperature conduction module.

Arrangement for placing central processors and memory in a cryo cooled

This error checker determines if more than one set of control signals F1 through FN are on and also flags invalid as opposed to valid situations where none of the control signals F1 to FN are on. To distinguish the invalid from valid situations where none of the control signals F1 to FN are on, an additional control signal X=F1.multidot.F2.multidot. . . . .multidot.FN is generated and then fed with the control signals F1 to FN through a prior art detector which detects when more than one or none of the control signals X and F1 through FN are on.

Error checking of mutually-exclusive control signals

A high speed multiply apparatus minimizes latch requirements and I/O pin requirement between chips by a new configuration which iteratively adds four multiples of a multiplicand in a stage of 4-2 carry save adders which then feed four-bit parallel adders each having four sum outputs and a carry output from the highest order bit position. Only the sum outputs are latched and then fed to a carry propagate adder on each iteration for addition to the previous partial products. Only the single carry output from each of the 4-bit parallel adders needs to be latched and then fed to another 4-bit parallel adder.

High speed multiplier using carry-save/propagate pipeline with sparse

An improved system for adding two numbers together. The numbers may be expressed either in binary form or in binary coded decimal form (wherein each decimal digit is represented by its equivalent four binary bits). By taking advantage of 'don't care' decimal input conditions, a minimal implementation of a carry look-ahead adder which can operate upon both types of numbers is obtained.

Integrated binary-BCD look-ahead adder

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Poughkeepsie, NY, United States of America

Samuel R Levine