International Business Machines Corporation

Samuel Kahn

Robert Allen Hood

Richard Dale Hoffman

Michael Ian Davis

Raymond Morris Bryant

Richard Eugene Birney

Lynn Allan Graybiel

William Steese Osborne

A method of determining Internet delays associated with requests from a Web client connectable to a Web server. The method begins at the Web server in response to a first HTTP request. In particular, the Web server serves a response to the first HTTP request and logs a server processing time associated with serving that response. After the response is delivered back to the Web client that initiated the request, an end user response time associated with the first HTTP request is calculated at the Web client. Upon a new HTTP request (typically the next one), the end user response time associated with the first HTTP request is then passed from the Web client to the Web server in a cookie. The Internet delay associated with the first HTTP request is then calculated by subtracting the server processing time from the end user response time.

World wide web internet delay monitor

A method of logging information in a computer network having a Web client connectable to a Web server. In response to the HTTP request (and as a result of receiving a response to that request), a response time associated with that first HTTP request is calculated. Thereafter, the response time calculated is passed from the Web client on a subsequent HTTP request to that Web server, where the information is logged for later use. In a preferred embodiment, the response time associated with the first HTTP request is passed in a cookie of the second HTTP request.

World wide web end user response time monitor

The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

Address key register load/store instruction system

Active address keys (AAK) are translated into respective addressabilities in physical main memory. Each addressability comprises one or more physical blocks which may be scattered in the main memory. Each address key represents the assigned addressability in main memory for a logical address space. Plural key register sections may be loaded with the same or different address keys. For each storage access request, received from a processor or I/O channel, AAK select circuits outgate to the translator the key in the key register section corresponding to the type of the current storage access request to determine the addressability available to the access request. Each address key identifies a particular stack of one or more segmentation registers. Each segmentation register can be assigned the address of any segment (i.e. a block of contiguous physical addresses located anywhere in the main memory). Each segmentation register also has validity and read-only flag bits for its assigned block. Each stack can translate a contiguous set of logical addresses into physical addresses. For each storage access request for a logical address, and not apparent to the usury program, a stack is addressed by the AAK to translate the logical address to a real address within the assigned addressability. Then a register in the stack is selected by high-order bits in the logical address. The addressed register outputs an assigned block address. Low order bits in the logical address select a byte address in the assigned block. The main memory can have any physical size, which is coordinated with the number of stacks, and to the number of segmentation registers in each stack.

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Mountain View, CA, United States of America

Samuel Kahn