Amazon Technologies, Inc.

Nicira, Inc.

Samuel Jacob

Mohammad El-Shabani

Ilya Minkin

Aditya Krishna Sonthy

Subin Cyriac Mathew

Drazen Borkovic

Yu Zhou

Srikar Tati

Alex Tessmer

Ron Diamant

Ganesan Chandrashekhar

Boon Seong Ang

Alexander Tessmer

Richard John Heaton

Rajeev Nair

Hongwei Zhu

Techniques are disclosed for setting a breakpoint for debugging a neural network. User input is received by a debugger program executable by a host processor indicating a target layer of a neural network at which to halt execution of the neural network. The neural network includes a first set of instructions to be executed by a first execution engine and a second set of instructions to be executed by a second execution engine. A first halt point is set within the first set of instructions and a second halt point is set within the second set of instructions. It is then determined that operation of the first execution engine and the second execution engine has halted. It is then determined that the first execution engine has reached the first halt point. The second execution engine is then caused to move through instructions until reaching the second halt point.

Breakpoints in neural network accelerator

Embodiments include techniques for enabling execution of N inferences on an execution engine of a neural network device. Instruction code for a single inference is stored in a memory that is accessible by a DMA engine, the instruction code forming a regular code block. A NOP code block and a reset code block for resetting an instruction DMA queue are stored in the memory. The instruction DMA queue is generated such that, when it is executed by the DMA engine, it causes the DMA engine to copy, for each of N inferences, both the regular code block and an additional code block to an instruction buffer. The additional code block is the NOP code block for the first N&#x2212;1 inferences and is the reset code block for the Ninference. When the reset code block is executed by the execution engine, the instruction DMA queue is reset.

Dynamic code loading for multiple executions on a sequential processor

An approach for improving throughput for encapsulated network traffic is provided. In an embodiment, a method comprises obtaining a plurality of network addresses of a plurality of intermediaries that facilitate communications between a plurality of virtual machines. A set of source-destination intermediary pairs is determined based on the plurality of network addresses, and for each source-destination intermediary pair, from the set of source-destination intermediary pairs, a precomputed encapsulated header is generated and included in a set of precomputed encapsulated headers. If a data packet from a particular source intermediary and destined to a particular destination intermediary is received, and a particular precomputed encapsulated header for the particular source intermediary and the particular destination intermediary is included in the set of precomputed encapsulated headers, then the particular precomputed encapsulated header is retrieved from the set of precomputed encapsulated headers and used to form a particular encapsulated packet.

Method for improving throughput for encapsulated network traffic

Systems and methods for non-intrusive hardware profiling are provided. In some cases integrated circuit devices can be manufactured without native support for performance measurement and/or debugging capabilities, thereby limiting visibility into the integrated circuit device. Understanding the timing of operations can help to determine whether the hardware of the device is operating correctly and, when the device is not operating correctly, provide information that can be used to debug the device. In order to measure execution time of various tasks performed by the integrated circuit device, program instructions may be inserted to generate notifications that provide tracing information, including timestamps, for operations executed by the integrated circuit device.

Non-intrusive hardware profiling

Described herein are systems, methods, and software to enhance flow operations on a host computing system. In one implementation, a virtual switch on a host identifies a packet from a virtual node. In response to identifying the packet, the virtual switch determines whether the packet corresponds to a cached result action based on traits of the packet. If the packet corresponds to a cached result action, then the virtual switch may process the packet in accordance with the cached result action. In contrast, if the packet does not correspond to a cached result action, then the virtual switch may process the packet in accordance with first flow operations to determine a result action, and cache the result action for use with future packets.

Caching flow operation results in software defined networks

Growing community of inventors

Fremont, CA, United States of America

Samuel Jacob