Avnera Corporation

Tektronix, Inc.

Other

Null Networks LLC

Samuel J Peters, Ii

Victor Lee Hansen

Eric P Etheridge

Alexander C Stange

Paul M Gerlach

Erik Landerholm

Kenneth P Dobyns

Steven K Sullivan

I Claude Denton

Donald C Kirkpatrick

Alfred C She

Robert C Proebstel

David P Maguire

Claude Denton

Victor Lee Hanson

Jing-Fan Zhang

A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a 'toothless' clock signal, wherein the sample counter is configured to be decremented by the 'toothless' clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the &#x201c;toothless&#x201d; clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.

SPDIF clock and data recovery with sample rate converter

A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a 'toothless' clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the 'toothless' clock signal to the sample rate converter.

A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated from the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.

Data transmission error reduction via automatic data sampling timing adjustment

In a network apparatus, control logic is provided to preemptively issue pause controls to a sender of network traffic of a link to preemptively regulate a rate the sender may send network traffic of the link. In one embodiment, the pause controls are sent periodically, with each including a pause duration. In one embodiment, at least a selected one of the pause duration and the periodicity of preemptive issuance is determined based at least in part on at least a selected one of a working capacity of storage medium allocated to service the link, a network traffic drain rate of the link, and a fill rate of the input line over which the network traffic of the link is received. In one embodiment, the networking apparatus is an optical networking module with the control logic disposed in a multi-protocol networking processor of the module.

Preemptive network traffic control for regional and wide area networks

A method and apparatus in which a plurality of demux processors propagates respective received sample streams to adjacent demux processors via an inter-demux bus; and wherein a final one of the plurality of demux processors propagates all of the respective received sample streams toward a next processing element such as a multi-drop bus (MDB) or system processor within a data acquisition device.

Inter-demux communication through a point to point interface

A method for rasterization of a set of voltage-versus-time data-address pairs into horizontal and vertical locations of a multi-bit raster display memory of a digital oscilloscope or similar electronic data acquisition instrument is disclosed. It provides a new way of controlling digital intensity, by allowing the operator and/or a function based on the instrument's trigger rate to set the number of intensity units available for brightening the pixels affected by the rasterization of each acquisition data pair. If a vector has more pixels than there are units of intensity available, the number of pixels that are to be brightened is limited but spread out over the vector's length by an algorithm that includes at least some degree of randomization. If there are more units of intensity available than there are pixels to put them in, the extra ones can either be distributed into each pixel or randomly added along the vector or ignored. If the vector has no length, all of the available intensity, or some lesser amount of intensity, is put on one pixel. Setting a small minimum vector length, below which only limited vector fill is used, can save time by limiting the amount spent on insignificant details. Setting maximum and minimum intensity levels for those pixels that are affected by the rasterization process can limit saturation and assure that areas that receive only one or a few attacks will still have an intensity level that is perceptible. Sparse vector rasterization avoids the hard binary choice between using a dot mode or a vector mode, and gives the user an analog-like intensity control that produces a perceived continuum of viewing choices. It does this while maximizing the number of pixels updated within the context of how many waveforms are being acquired and need to be processed.

Sparse vector rasterization

A SONET path/ATM physical layer transmit/receive processor ASIC for OC-48 makes use of a 32-bit wide interface between a source/destination and the rest of the processor. Adjacent the interface is an ATM cell processor, and between the ATM cell processor and a transmission medium is a SONET payload processor. Selectors are located between the transmission medium and the SONET payload processor, the SONET payload processor and the ATM cell processor, and the ATM cell SONET path/ATM physical layer path, an ATM physical layer path or a fast FIFO buffer path according to the configuration of the selectors determined by user commands from a command logic circuit coupled to each of the interface, ATM cell processor and the SONET payload processor.

Growing community of inventors

Beaverton, OR, United States of America

Samuel J Peters, Ii