Nvidia Corporation

Hewlett-packard Development Company, L.p.

Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Other

Samuel Hammond Duncan

Jerome Francis Duluk, Jr

James Leroy Deming

Mark Hairgrove

Cameron Buschardt

Lucien Dunning

John Mashey

Lukito Muliadi

Raymond Hoi Man Wong

Lacky V Shah

Robert T George

Chenghuan Jia

Arvind Gopalakrishnan

Madhukiran V Swarna

Sherry Cheung

Jonathon Stuart Ramsey Evans

Mark Douglas Hummel

John H Edmondson

Wishwesh Anil Gandhi

David W Hartwell

Wei-Je Robert Huang

Gregory Scott Palmer

Lincoln G Garlick

Shailendra Singh

Alan Menezes

Manas Mandal

Praveen Joginipally

Pranav Vaidya

Feiqi Su

Timothy John Purcell

Vyas Venkataraman

Paul Michael Guglielmi

Steven Ho

Craig Durand Keefer

Dennis K Ma

Jonathon Stuart Ramsay Evans

Glenn Arthur Herdeg

Eric Rock

Richard Eugene Kessler

David Brian Glasco

Sean Jeffrey Treichler

Patrick Rene Marchand

Olivier Giroux

Brian Matthew Fahs

Glenn A Dearth

Paolo Enrique Sabella

Sanjeev Jain

Philip Browning Johnson

Denis J Foley

Larry Robert Dennison

John R Feehrer

Ricky C Hetherington

Brian Kelleher

Steve Lang

David T Mayo

Ram Gummadi

Gary Ward

Hemayet Hossain

David A J Webb, Jr

Alexander Toichi Ishii

Nir Haim Arad

Andrej Kocev

Maurice Bennet Steinman

Thomas Adam McLaughlin

Sonata Gale Wen

Steven E Molnar

Robert Anthony Alfieri

Peter C Mills

Donald W Smelser

Darrel D Donaldson

Daniel Elliot Wexler

Dane Mrazek

Richard A Silkebakken

Colin E Brench

David William Nuechterlein

Richard E Olson

Robert J Hasslen

David Golden

Ravi Kiran Manyam

Jeffrey M Smith

Michael Asbury Woodmansee

Jeff Tuckey

Paul C Wade

Jay Gupta

Yin Fung Tang

Jonathan Owen

M Wasiur Rashid

Dennis D Hayes

Stephen E Lindquist

Mike Osborn

Rajen S Ramchandani

Wojciech Jan Truty

Atul Kalambur

Prakash G Apte

Radha Kanekal

Frederick C Canter

Jeffrey Willcox

Roger Pannel

Rafal Zboinski

Dennis Francis Hayes

A parallel processing unit (PPU), operating in a traditional processing environment or in a virtualized processing environment, can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

Techniques for configuring a processor to function as multiple, separate processors in a virtualized environment

A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.

Techniques for configuring a processor to function as multiple, separate processors

Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.

Techniques for an efficient fabric attached memory

A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Fault buffer for tracking page faults in unified virtual memory system

Techniques for reconfiguring partitions in a parallel processing system

Multiprocessor clusters in a virtualized environment conventionally fail to provide memory access security, which is frequently a requirement for efficient utilization in multi-client settings. Without adequate access security, a malicious process may access what might be confidential data that belongs to a different client sharing the multiprocessor cluster. Furthermore, an inadvertent programming error in the code for one client process may accidentally corrupt data that belongs to the different client. Neither scenario is acceptable. Embodiments of the present disclosure provide access security by enabling each processing node within a multiprocessor cluster to virtualize and manage local memory access and only process access requests possessing proper access credentials. In this way, different applications executing on a multiprocessor cluster may be isolated from each other while advantageously sharing the hardware resources of the multiprocessor cluster.

Securing memory accesses in a virtualized environment

Distributed address translation in a multi-node interconnect fabric

Fault buffer for resolving page faults in unified virtual memory system

Techniques are disclosed for performing an auxiliary operation via a compute engine associated with a host computing device. The method includes determining that the auxiliary operation is directed to the compute engine, and determining that the auxiliary operation is associated with a first context comprising a first set of state parameters. The method further includes determining a first subset of state parameters related to the auxiliary operation based on the first set of state parameters. The method further includes transmitting the first subset of state parameters to the compute engine, and transmitting the auxiliary operation to the compute engine. One advantage of the disclosed technique is that surface area and power consumption are reduced within the processor by utilizing copy engines that have no context switching capability.

Replicated stateless copy engine

Migration scheme for unified virtual memory system

A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory.

Method and system for implementing multi-stage translation of virtual addresses

Growing community of inventors

Arlington, MA, United States of America

Samuel Hammond Duncan