Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Samuel Evain

Valentin Gherman

Bastien Giraud

Yannick Bonhomme

An electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder. An electroforming device performing electroforming through write operations to such a resistive memory and to a method for checking a write operation.

Electroforming process using an inversion-invariant linear ECC, and associated device

A method for selectively inverting a word to be written to a memory is provided. The memory includes memory cells, each memory cell allowing at least two values associated with at least one bit to be stored, the decision as to whether to invert a word being made depending on a number of vulnerable values, which number is determined on the basis of the data bits, of the inversion bit and of uneven check bits.

Method for selectively inverting words to be written to a memory and device for implementing same

A method is provided for generating a maximized linear correcting code from a base linear correcting code, the base correcting code and the maximized linear correcting code being associated with one and the same parity matrix H, the matrix being used to generate syndromes, the syndromes being used for decoding code words. The method comprises a step of identifying the syndromes unused for decoding the base linear correcting code, a step of identifying the errors that can affect the code words and make it possible to obtain the unused syndromes when a code word is multiplied by the matrix H and a step of selecting a unique error for each unused syndrome from among the identified errors, the error being called additional error.

Method for generating a maximized linear correcting code, method and device for decoding such a code

A device for correcting an initial binary word affected by an error in 1 or 2 bits and arising from a corrector code endowed with a minimum Hamming distance of 3 or 4, comprises first means for correcting an error of 1 bit and for detecting an error of more than 1 bit in the initial word and second means for correcting an error of 1 bit in a word arising from an inversion module, able to receive a datum indicative of a binary level of confidence, low or high, assigned to each of the bits of at least one part of the initial word, said inversion module being configured to invert the bits of the initial word which suffer the low confidence level, and a multiplexer with at least two inputs which is driven by the means for detecting an error of more than 1 bit in the initial word, said multiplexer being fed on a first input by the output of the first correction means and on a second input by the output of the second correction means.

Device for correcting two errors with a code of hamming distance three or four

An error-correcting coding method generates code words of m bits from useful data blocks of n bits. The method adds k check bits to a block of n useful data bits in order to generate a code word of m=n+k bits, said check bits being defined according to the combination rules defined by a parity matrix H consisting of binary elements and having k rows and m columns such that H&#xb7;V=0, V being a column matrix whose m elements are the m bits of the code word to be generated. The k check bits are separated into two groups, on the one hand a group of k1 bits called total parity bits PT and on the other hand a group of k2 bits called conventional check bits VC, the values of k, k1 and k2 satisfying the conditions k=k1+k2 and k&#x3e;k1&#x3e;2, the matrix H whose columns can be swapped being broken down into six submatrices A, B, C, D, E and F. Another method detects multiple errors in code words generated by the coding method.

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Saclay, France

Samuel Evain