Microchip Technology Inc.

Checkpoint Systems, Inc.

Microchip Technologies, Inc.

Samuel E Alexander

Richard J Fisher

Kent D Hewitt

Lee Furey

William F Gallagher, Iii

Youbok Lee

Shinichiro Inui

Ronald Salesky

Riccardo Benedetti

Ezana Haile Aberra

Bruce Edward Beauchamp

David Francis Mietus

Stephen Loyer

Stephen V Drehobl

Leonard F French

An input voltage range may be established between different voltage levels used for different programming functions of an integrated circuit device, thus implementing a protection zone ('safe zone') of non-operation to facilitate prevention of an unintended irreversible programming operation, e.g., permanent write protection.

Preventing unintended permanent write-protection

Arbitration of multiple transponders, such as RFID tags, occurs in an interrogation field. The arbitration process is custom-tailored for individual applications, under software control, by the transponder reader or tag reader. Different wake-up slots are calculated for each tag during successive transmission cycles based upon the tag ID and the transmission cycle number. The tag reader may also send a special command to a tag to read its data and cause the tag to become decoupled from the environment. The tags may be selectively placed in either a tag-talk-first mode or a reader-talk-first mode. Furthermore, the tag reader may send a special fast read command to the tag which includes a read request and at least one parameter of the read request.

Anticollision protocol with fast read request and additional schemes for reading multiple transponders in an RFID system

Arbitration of multiple transponders, such as RFID tags, occurs in an interrogation field. The arbitration process is custom-tailored for individual applications, under software control, by the transponder reader or tag reader. Different wake-up slots are calculated for each tag during successive transmission cycles based upon the tag ID and the transmission cycle number. The tag reader may send a special fast read command to the tag which includes a read request and communications control parameters including the number of time slots for transponder communications, the number of transmissions that an individual transponder is allowed to issue, and the data rate at which the reader communicates to the transponder. The tag reader may also send a special command to a tag to read its data and cause the tag to become decoupled from the environment. Additional schemes are provided to halve the number of active tags in each transmission cycle and to selectively inactivate designated groupings of tag, thereby improving discrimination of the tags in the interrogation field. The tags may be selectively placed in either a tag-talk-first mode or a reader-talk-first mode.

A radio frequency identification (RFID) tag device having a pulse position modulation (PPM) decoder circuit which calculates a relative frequency relationship between an internal oscillator of the RFID tag device and an external PPM source such as a RFID tag reader. The PPM decoder circuit is calibrated to the difference between the external PPM frequency source (i.e., RFID tag reader) and the internal clock-oscillator of the RFID tag device, which is performed in a single measurement during one calibration symbol period.

Method, system and apparatus for calibrating a pulse position modulation (PPM) decoder to a PPM signal

A sequential memory device having a read pipeline data structure for reading data from a bitline of a memory array of the device is disclosed. The read pipeline data structure includes at least one data path including a sense amp for sensing the logic level appearing on the bitline, a flip-flop for providing an output signal indicative of the data bits received on the bitline, and means for initializing the data path upon power up of the device such that the first data bit from the memory array is available for output from the device without the need and before the occurrence of a clock signal.

Initializing a read pipeline of a non-volatile sequential memory device

An I.sup.2 C bus-compatible, serial EEPROM device is used in applications involving storage and serial transmission of configuration and control information for an intelligent peripheral device with which the EEPROM device is associated, for communication on a bus to a host device adapted to control the peripheral device. The EEPROM device has a memory array for storing data representing the configuration and control information. Two modes of data transmission are supported by the EEPROM device, and are alternately and selectively established according to whether data stored in the EEPROM array is to be read only, by sequential output onto the bus, or the array is also to be allowed to be written to. The arrangement ultimately allows intelligent interaction between the host device and the peripheral device. A separate clock line supplements the usual clock line and data line of an I.sup.2 C bus to support the distinct and different modes, with clocking by the respective clock line for the established mode. A controlled multiplexer selectively connects the input clock according to a predetermined logic level transition on one of the two clock lines.

Memory device with switching of data stream modes

A serial EEPROM (electrically erasable programmable read only memory) device and method for reducing the time required to load data into the serial EEPROM device using a special write cache are disclosed. The EEPROM has an internal memory array for receiving a burst of data sent by a microcontroller. Data in the burst of data is initially loaded into an SRAM (static random access memory) write cache where it is stored sequentially and grouped in a plurality of pages, so that the bus and the microcontroller are freed to allow the microcontroller to perform other processing tasks at least until the EEPROM memory is written and the EEPROM is again accessible to the microcontroller. Writing of the internal memory array is accomplished sequentially with data from the pages of the cache loaded into rows of the internal memory array until the cache is depleted, the pages being sized so that an integral number of pages is stored in each row of the internal memory array.

Serial EEPROM device and associated method for reducing data load time

Power consumption of a serial EEPROM is reduced while simultaneously precluding data corruption during write operations. These results are achieved by operating a brownout detector in the device to sense EEPROM supply voltage below a predetermined level and thereupon to place the EEPROM in a reduced power mode, but only during an interval that a write sequence is taking place. Such an interval includes loading of data in a temporary storage cache and writing the loaded data into the EEPROM. At the same time that the low voltage level is detected during a write sequence, any load or write operation then in progress is aborted. The brownout detector is intentionally left disabled or in a sleep mode during any read mode or standby mode since there is no jeopardy of corrupting the EEPROM memory during those times.

Power management system for serial EEPROM device

An erasable programmable memory device has a number of data storage blocks. Each block has an endurance characteristic that at least roughly defines the number of times data may be erased from and written to the block before it wears out in that data cannot then be further erased from and written to the block. A redundant data storage block of memory capacity and endurance similar to that of each of the other data storage blocks is disposed in parallel with a selected one of the latter for which higher endurance is desired. This enables identical data to be written simultaneously to the two blocks and thus considerably increases the endurance of the selected block by virtue of the fact that identical memory cells in both blocks must fail before the endurance of the selected block will be depleted. After the selected block has been designated for high endurance and placed in parallel with the redundant block, a fuse may be set to prevent alteration of that designation.

Programmable high endurance block for EEPROM device

An erasable programmable memory device has a number of contiguous data storage cells forming the data memory of the device. The address of one of these data storage cells is stored to designate it as a cell which is to be write protected so that its contents may not thereafter be erased or overwritten. Information is also stored to identify the total number of contiguous data storage cells to be similarly write protected commencing with the cell whose address is stored to designate write protection. The contents of the designated and identified cells are then made permanent. Write protection of the designated and identified cells is accomplished by comparing each write operation address with the addresses of the data storage cells encompassed within the protected area, and if it is within that area, aborting the write operation.

Write protection security for memory device

The usability of an electrically erasable programmable semiconductor memory device is assured after shipment from the factory despite implementing the device with a user option to selectively configure the security, endurance, organization, density or protocol of the memory array of the device. The user selected configuration is made permanent and inaccessible for change by programming associated normally reversible configuration fuses which are rendered incapable of being reprogrammed (reversed) thereafter by the automatic and simultaneous programming of a lockout fuse. Final testing of the device at the factory is permitted by an override of the lockout fuse during testing of the operation of the configuration fuses, and, when the testing is completed, returning, under program control, all fuses to a default condition in which the configuration fuses are limited to one-time programmability as a consequence of automatic simultaneous programming of the lockout fuse and configuration fuses at any time after shipment of the device from the factory.

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Gilbert, AZ, United States of America

Samuel E Alexander