Raytheon Company

Samuel Doug Tonomura

Clifton Quan

Mark S Hauhe

Tse E Wong

Ethan Santosh Heinrich

Stephen E Sox

Timothy E Dearden

Anthony M Petrucelli

Polwin C Chan

Cynthia Y Hang

Robert Chris Allison

Brian M Pierce

John G Heston

Chad E Patterson

Michael M Fitzgibbon

John Fraschilla

Mark A Talcott

A quasi-switched, multi-band, high-power amplifier includes an input matching network, a low band path, a high band path, and an output matching network. The input matching network includes a single input port that is configured to receive an input signal. The input signal includes at least one tone within a specified frequency band. The low band path is configured, when the specified frequency band is a low frequency band, to amplify the input signal to generate a low band amplified signal. The high band path is configured, when the specified frequency band is a high frequency band, to amplify the input signal to generate a high band amplified signal. The output matching network includes a single output port and is configured to filter at least one of the low band amplified signal and the high band amplified signal into a load through the single output port.

Quasi-switched, multi-band, high-power amplifier and method

An integrated circuit system having: (A) a semiconductor chip with a signal strip conductor disposed on an upper surface of the chip; an active semiconductor device disposed of the upper surface of the chip electrically connected to the signal strip conductor; and a first ground plane conductor disposed on a bottom surface of the chip disposed under the signal strip conductor; and (B) a support structure having: a second ground plane disposed over, and separated from, the signal strip conductor by a dielectric region between the second ground plane and the signal strip conductor on the chip; a signal contact disposed on the bottom surface of the support structure displaced, electrically insulated, from the second ground plane conductor, and electrically connected to a portion of the signal strip conductor. The signal strip conductor, the first ground plane conductor, and the second ground plane conductor provide a stripline microwave transmission line.

Integrated circuit system having stripline structure

A system for improving flip chip performance is provided. In one embodiment, the invention relates to an assembly configured to improve performance of a flip chip device, the assembly including a semiconductor die having an active surface and a back surface, the active surface including a plurality of conductive pads, an interposer substrate having a first surface in electrical contact with the active surface of the semiconductor die and a second surface, a space between the active surface of the semiconductor die and the first surface of the interposer substrate, where the space is essentially free of underfill material, and a carrier substrate having a top surface in electrical contact with the second surface of the interposer.

System for improving flip chip performance

In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

Stacked integrated circuit assembly

A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

A hybrid assembly having improved cross talk characteristics includes an electromagnetic band gap (EBG) layer on a substrate having an upper surface and a lower surface and a semiconductor structure (MMIC) mounted above the EBG layer. A plurality of stars made of an EBG material are preferably printed, or deposited, on the upper surface. The EBG material has slow wave characteristics. The plurality of stars tessellates the upper surface between conductive paths. Each of the stars has a center section formed from a regular polygon, the center section having projections extending from the center section. The projections and the center section form a periphery. The periphery engages adjacent stars along the periphery. Stars are separated from adjacent stars by an interspace. Each of the stars is connected to a conductive via, in turn connected to ground potential. A conductive layer at ground potential is electrically continuous with vias used to interconnect all stars forming the EBG layer.

Periodic interleaved star with vias electromagnetic bandgap structure for microstrip and flip chip on board applications

A first MEM is mounted on a substrate having a first contact and a second contact is mounted on a substrate. A PA power cell is thermally connected to the substrate using a thermal bump. The power cell is electrically insulated from the substrate. The power cell has a first power cell bump and a second power cell bump as pathways for I/O functions. A first insulator is mounted on the substrate supporting a second MEM above the substrate. The second MEM has a first connection and a second connection The first connection and the second connection are located on a bottom surface of the second MEM. A first conductive via vertically traverses the first insulator and is connected to the first connection from the second MEM. This first conductive via is further connected to a first conductor. The first conductor is insulated from substrate by a first insulating layer. The first conductor is further connected to the first power cell bump. A second conductor is insulated from the substrate by a second insulating layer. The second conductor is connected to a second conductive via. The second conductive via traverses vertically a second insulator. The second conductive via is connected to a first metal member. The first metal member is formed over the upper surface of the second insulator and connected to a first input to the first MEM switch. A second metal member is connected to the second contact of the first MEM switch. The second metal member is formed over the upper surface of a third insulator. The third insulator is positioned over the substrate.

Growing community of inventors

Rancho Palos Verdes, CA, United States of America

Samuel Doug Tonomura