Texas Instruments Corporation

Samuel D Pritchett

Francesco Dantoni

Jeffrey A Schlang

Anthony Louis Coyle

Milton Lee Buschbom

Alan R Holden

Sherif Embabi

Baseband processor and communication overloading can be relieved in a portable wireless communication terminal by decentralizing power control () and frequency shift control () functions that are conventionally concentrated in the baseband processor. A timing sequencer () for power control can be integrated into a transceiver of the portable wireless communications terminal, thereby advantageously permitting power control signals to be generated on the transceiver side () rather than the baseband processor side. Shadow registers () containing information indicative of commonly used or repeated frequencies can be integrated into the transceiver side, thereby advantageously relieving the baseband processor of corresponding frequency shift control responsibilities. These responsibilities can be further relieved by integrating into the transceiver side a sequencer () cooperable with the shadow registers for controlling frequency shifting of a frequency generator on the transceiver side, and by integrating into the transceiver side further shadow registers () for programming the sequencer with desired frequency shift sequences.

Wireless communications with transceiver-integrated frequency shift control and power control

An RF receiver apparatus () is provided physically separately from a cooperating baseband processor apparatus (). The RF receiver includes a mixer circuit () and an analog IF-to-digital baseband converter () formed on an integrated circuit. Sampling frequencies of the analog IF-to-digital baseband converter are controlled by the RF receiver apparatus.

If-to-baseband conversion for flexible frequency planning capability

A semiconductor device has passive components integrated with the circuit and encapsulated in a plastic package for solder ball or leaded attachment. A plastic chip-scale semiconductor device has a substrate made of a plurality of patterned insulating layers alternating with patterned electrically conductive layers, the layers mutually adhering to form the substrate. The layers include a plurality of passive electrical components, such as capacitors, inductors, and resistors, and routing lines. Most routing lines terminate in a first plurality of bondable contact pads and a second plurality of solderable contact pads. The components and lines form a web and are configured mostly in a narrow peripheral band at least partially around a central substrate area, and are operable with high performance in conjunction with an integrated circuit (IC) chip. The chip is attached to the central substrate area and electrically connected to the first plurality of contact pads, respectively, whereby the passive components are integrated with the IC. Plastic encapsulation material surrounds the chip, first plurality of contact pads, and passive components such that the outline of the material is approximately the same as the outline of the chip.

Plastic chip-scale package having integrated passive components

A discrete increment attenuator for processing an input signal by effecting discrete attenuation increments of the input signal to create corresponding attenuation states for the output signal resulting from the input signal, comprising a parallel branched attenuator network providing at least three attenuation states defining corresponding attenuation increments, coupled to receive the input signal and provide the output signal. A separate attenuation branch circuit having an input end and an output end corresponding to a particular plural parallel branch is selectively activated by an attenuation control signal for effecting a discrete incremental attenuation of the input signal. Control circuitry for each attenuation branch circuit is responsive to an attenuation control signal for selectively activating the associated attenuation branch circuit to effect the incremental attenuation including two active control elements, one on each end of each attenuation branch circuit, the attenuation state control signal biasing the active control elements one of both on to activate the branch circuit and effect the corresponding attenuation or both off to deactivate the branch circuit. Each attenuation branch circuit has two ends, a resistive T-network coupled between the two ends and an RF path which blocks DC bias voltages from the T-network to a source of reference voltage. A bias-off offset circuit is coupled to the input for providing an offset biasing level to the respective two control elements for each inactive branch circuit to inhibit those circuits from activating in response to extraneous signals.

Discrete increment signal processing system using parallel branched

A quasi-interdigitated transistor (50) for rf power applications has a plurality of channel regions (102-118) that are each offset from each other in a y-direction such that a q.sub.x heating component from adjacent channel regions will affect any one channel region to a lesser extent that the q.sub.x from adjacent channel regions in the conventional interdigitated structure. In a preferred embodiment, the channel regions (102-118) are formed in a single, curved, V-shaped row such that the cumulative transverse width of all of the transistor sections is less than the waveguide cutoff frequency. The V-shaped row of transistor sections also provides the advantage of parallel signal paths having approximately the same propagation time delay such that there is no phase cancellation within the device.

Thermally optimized interdigitated transistor

A parallel branched N-state design method is used for discrete increment signal processing systems, such as incremental phase shifters and attenuators. These systems are implemented using parallel branched signal processing networks, each with N parallel discrete increment branch circuits (i.e., without being restricted to binary-state networks). In comparison with conventional cascaded binary-state networks, the parallel branched N-state design achieves reduced complexity and insertion loss. An exemplary embodiment of a phase shift system providing 32 phase increments (or states) uses three cascaded phase shift networks--two quaternary-state networks (Quits 10, 20) and a single binary-state network (Bit 30). The most significant Quit (10) illustrates the N-state design, providing the four most significant phase states (reference, +90.degree., -180.degree., -90.degree.) using four switched-line branch circuits (100, 200, 300, 400), each controlled by two PIN diode control elements (D1A/D1B, D2A/D2B, D3A/D3B, D4A/D4B). A parallel branched N-state design for discrete increment systems minimizes insertion loss and complexity by minimizing the total number of cascaded networks, the total number of cascaded branch circuits and the total number of branch control elements.

A quasi-interdigitated transistor (50) for rf power applications has a plurality of channel regions (102-118) that are each offset from each other in a y-direction such that a q.sub.x heating component from adjacent channel regions will affect any one channel region to a lesser extent than the q.sub.x from adjacent channel regions in the conventional interdigitated structure. In a preferred embodiment, the channel regions (102-118) are formed in a single, curved, V-shaped row such that the cumulative transverse width of all of the transistor sections is less than the waveguide cutoff frequency. The V-shaped row of transistor sections also provides the advantage of parallel signal paths having approximately the same propagation time delay such that there is no phase cancellation within the device.

The disclosure relates to a dual gate FET used in variable power amplifiers wherein a gain control circuit is provided across the dual gate electrodes whereby the voltage on one of the gate electrodes is a function of the voltage on the other gate electrode.

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La Jolla, CA, United States of America

Samuel D Pritchett